메뉴 건너뛰기




Volumn 26, Issue 4, 2006, Pages 8-17

IPC considered harmful for multiprocessor workloads

Author keywords

[No Author keywords available]

Indexed keywords


EID: 33947715600     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2006.73     Document Type: Article
Times cited : (109)

References (14)
  • 4
    • 0036469676 scopus 로고    scopus 로고
    • Simics: A Full System Simulation Platform
    • Feb
    • P.S. Magnusson et al., "Simics: A Full System Simulation Platform," Computer, vol. 35, no. 2, Feb. 2002, pp. 50-58.
    • (2002) Computer , vol.35 , Issue.2 , pp. 50-58
    • Magnusson, P.S.1
  • 5
    • 33748870886 scopus 로고    scopus 로고
    • Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset
    • Nov
    • M.M.K. Martin et al., "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," ACM Sigarch Computer Architecture News, vol. 33, no. 4, Nov. 2005, pp. 92-99.
    • (2005) ACM Sigarch Computer Architecture News , vol.33 , Issue.4 , pp. 92-99
    • Martin, M.M.K.1
  • 6
    • 25844437046 scopus 로고    scopus 로고
    • Powers System Microarchitecture
    • B. Sinharoy et al., "Powers System Microarchitecture," IBM J. Research and Development, vol. 49, no. 4/5, 2005, pp. 505-522.
    • (2005) IBM J. Research and Development , vol.49 , Issue.4-5 , pp. 505-522
    • Sinharoy, B.1
  • 7
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-Way Multithreaded Spare Processor, vol. 25, no. 2
    • Mar.-Apr
    • P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32-Way Multithreaded Spare Processor," vol. 25, no. 2, IEEE Micro, Mar.-Apr. 2005, pp. 21-29.
    • (2005) IEEE Micro , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 10
    • 0036469652 scopus 로고    scopus 로고
    • SimpleScalar: An Infrastructure for Computer System Modeling
    • Feb
    • T. Austin et al., "SimpleScalar: An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, Feb. 2002, pp. 59-67.
    • (2002) Computer , vol.35 , Issue.2 , pp. 59-67
    • Austin, T.1
  • 14
    • 85008034312 scopus 로고    scopus 로고
    • Efficiently Evaluating Speedup Using Sampled Processor Simulation
    • Y. Luo and L.K. John, "Efficiently Evaluating Speedup Using Sampled Processor Simulation," IEEE Computer Architecture Letters, 2004, http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/letters/ca/ &toc=comp/letters/ca/2004/01/y1toc.xml& DOI=10.1109/L-CA.2004.6.
    • (2004) IEEE Computer Architecture Letters
    • Luo, Y.1    John, L.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.