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Volumn , Issue , 2004, Pages 45-56

A co-phase matrix to guide simultaneous multithreading simulation

Author keywords

[No Author keywords available]

Indexed keywords

CO-PHASE MATRIX; FOUR-THREADED WORKLOADS; SIMULTANEOUS MULTITHREADING (SMT) SIMULATION; WORKLOADS;

EID: 2642575180     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/ISPASS.2004.1291355     Document Type: Conference Paper
Times cited : (76)

References (16)
  • 3
    • 0003465202 scopus 로고    scopus 로고
    • The SimpleScalar tool set, version 2.0
    • University of Wisconsin, Madison, June
    • D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
    • (1997) Technical Report , vol.CS-TR-97-1342
    • Burger, D.C.1    Austin, T.M.2
  • 7
    • 1842849819 scopus 로고    scopus 로고
    • Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream
    • September
    • T. Lafage and A. Seznec. Choosing representative slices of program execution for microarchitecture simulations: A preliminary application to the data stream. In Workload Characterization of Emerging Applications, Kluwer Academic Publishers, September 2000.
    • (2000) Workload Characterization of Emerging Applications, Kluwer Academic Publishers
    • Lafage, T.1    Seznec, A.2
  • 8
    • 0013229812 scopus 로고    scopus 로고
    • Thread-sensitive scheduling for SMT processors
    • University of Washington
    • S. Parekh, S. Eggers, and H. Levy. Thread-sensitive scheduling for SMT processors. Technical report, University of Washington, 2000.
    • (2000) Technical Report
    • Parekh, S.1    Eggers, S.2    Levy, H.3
  • 13
    • 0033220924 scopus 로고    scopus 로고
    • Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques
    • November
    • K. Skadron, P. Ahuja, M. Martonosi, and D. Clark. Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers, 48(11):1260-81, November 1999.
    • (1999) IEEE Transactions on Computers , vol.48 , Issue.11 , pp. 1260-1281
    • Skadron, K.1    Ahuja, P.2    Martonosi, M.3    Clark, D.4
  • 15
    • 0029666641 scopus 로고    scopus 로고
    • Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
    • D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ISCA, pages 191-202, 1996.
    • (1996) ISCA , pp. 191-202
    • Tullsen, D.M.1    Eggers, S.J.2    Emer, J.S.3    Levy, H.M.4    Lo, J.L.5    Stamm, R.L.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.