-
1
-
-
0038346244
-
SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
-
June
-
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, in Proceedings of the 30th Annual International Symposium on Computer Architecture, pp. 84-95 (June 2003).
-
(2003)
Proceedings of the 30th Annual International Symposium on Computer Architecture
, pp. 84-95
-
-
Wunderlich, R.E.1
Wenisch, T.F.2
Falsafi, B.3
Hoe, J.C.4
-
3
-
-
0024656760
-
An analytical cache model
-
May
-
A. Agarwal, M. Horowitz, and J. Hennessy, An Analytical Cache Model, ACM Transactions on Computer Systems, 7(2):184-215 (May 1989).
-
(1989)
ACM Transactions on Computer Systems
, vol.7
, Issue.2
, pp. 184-215
-
-
Agarwal, A.1
Horowitz, M.2
Hennessy, J.3
-
4
-
-
0028013968
-
Trace driven simulation using sampled traces
-
Architecture, January
-
J. W. C. Fu and J. H. Patel, Trace Driven Simulation using Sampled Traces, in Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences, Vol. I, Architecture, pp. 211-220, (January 1994).
-
(1994)
Proceedings of the Twenty-seventh Hawaii International Conference on System Sciences
, vol.1
, pp. 211-220
-
-
Fu, J.W.C.1
Patel, J.H.2
-
5
-
-
0032666383
-
On the use of trace sampling for architectural studies of desktop applications
-
May
-
P. Crowley and J. L. Baer, On the Use of Trace Sampling for Architectural Studies of Desktop Applications, in Proceedings of the 1999 SIGMETRICS Conference, pp. 208-209 (May 1999).
-
(1999)
Proceedings of the 1999 SIGMETRICS Conference
, pp. 208-209
-
-
Crowley, P.1
Baer, J.L.2
-
7
-
-
0005369980
-
Precise and accurate processor simulation
-
February
-
H. W. Cain, K. M. Lepak, B. A. Schwartz, and M. H. Lipasti, Precise and Accurate Processor Simulation, in 5th Workshop On Computer Architecture Evaluation Using Commercial Workloads (CAECW), (February 2002).
-
(2002)
5th Workshop on Computer Architecture Evaluation Using Commercial Workloads (CAECW)
-
-
Cain, H.W.1
Lepak, K.M.2
Schwartz, B.A.3
Lipasti, M.H.4
-
8
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
October
-
T. Sherwood, E. Perelman, G. Hamerly, and B. Calder, Automatically Characterizing Large Scale Program Behavior, in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems pp. 45-57 (October 2002).
-
(2002)
Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems
, pp. 45-57
-
-
Sherwood, T.1
Perelman, E.2
Hamerly, G.3
Calder, B.4
-
10
-
-
0024107186
-
Accurate low-cost methods for performance evaluation of cache memory systems
-
November
-
S. Laha, J. H. Patel, and R. K. Iyer, Accurate Low-cost Methods for Performance Evaluation of Cache Memory Systems, IEEE Transactions on Computers, 37(11): 1325-1335 (November 1988).
-
(1988)
IEEE Transactions on Computers
, vol.37
, Issue.11
, pp. 1325-1335
-
-
Laha, S.1
Patel, J.H.2
Iyer, R.K.3
-
12
-
-
0028445155
-
A comparison of trace-sampling techniques for multi-megabyte caches
-
R. E. Kessler, M. D. Hill, and D. A. Wood, A comparison of Trace-sampling Techniques for Multi-megabyte Caches, IEEE Transactions on Computers, 43(6):pp. 664-675 (1994).
-
(1994)
IEEE Transactions on Computers
, vol.43
, Issue.6
, pp. 664-675
-
-
Kessler, R.E.1
Hill, M.D.2
Wood, D.A.3
-
13
-
-
0030645301
-
Accuracy and speed-up of parallel trace-driven architectural simulation
-
April
-
A. T. Nguyen, P. Bose, K. Ekanadham, A. Nanda, and M. Michael, Accuracy and Speed-up of Parallel Trace-driven Architectural Simulation, in Proceedings of the 11th International Parallel Processing Symposium (IPPS'97), pp. 39-44, (April 1997).
-
(1997)
Proceedings of the 11th International Parallel Processing Symposium (IPPS'97)
, pp. 39-44
-
-
Nguyen, A.T.1
Bose, P.2
Ekanadham, K.3
Nanda, A.4
Michael, M.5
-
15
-
-
1842860792
-
Accurately warmed-up trace samples for the evaluation of cache memories
-
Orlando, Florida
-
L. Eeckhout, S. Eyerman, B. Callens, and K. De Bosschere, Accurately Warmed-up Trace Samples for the Evaluation of Cache Memories, in High Performance Computing Symposium 2003, Orlando, Florida, pp. 267-274, (2003).
-
(2003)
High Performance Computing Symposium 2003
, pp. 267-274
-
-
Eeckhout, L.1
Eyerman, S.2
Callens, B.3
De Bosschere, K.4
-
16
-
-
25844526328
-
BLRL: Accurate and efficient warmup for sampled processor simulation
-
L. Eeckhout, Y. Luo, K. De Bosschere, and L. K. John, BLRL: Accurate and Efficient Warmup for Sampled Processor Simulation, The Computer Journal, 48(4): 451-459 (2005).
-
(2005)
The Computer Journal
, vol.48
, Issue.4
, pp. 451-459
-
-
Eeckhout, L.1
Luo, Y.2
De Bosschere, K.3
John, L.K.4
-
17
-
-
84861243644
-
-
time July
-
SimpleScalar LLC. http://www.simplescalar.com/access time July 2003
-
(2003)
-
-
-
18
-
-
0003465202
-
The simpleScalar tool set, version 2.0
-
Computer Sciences Department, University of Wisconsin-Madson June
-
D. Burger and T. M. Austin, The SimpleScalar Tool Set, Version 2.0, Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madson (June 1997).
-
(1997)
Technical Report
, vol.1342
-
-
Burger, D.1
Austin, T.M.2
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