Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis

2008 IEEE International Symposium on Workload Characterization, IISWC'08

Volumn , Issue , 2008, Pages 163-172

  Hughes, Clay ^a   Li, Tao ^b  

^a Intelligent Design of Efficient Architecture Lab(IDEAL)

^b University of Florida

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE DESIGNS; AUTOMATICALLY GENERATE; AVERAGE NUMBERS; COMPLEX ARCHITECTURES; COMPLEX CHARACTERISTICS; COMPLEX INTERACTIONS; CORE PROCESSORS; DESIGN ALTERNATIVES; EXISTING METHODS; FLOW GRAPHS; MACHINE LEARNINGS; MEMORY ACCESSES; MICROBENCHMARKS; MICROPROCESSOR ARCHITECTURES; MULTIPLE THREADS; NEW TECHNIQUES; PERFORMANCE EVALUATIONS; REFERENCE MODELS; STATISTICAL SAMPLINGS; STATISTICAL SIMULATIONS; SYNTHESIS TECHNIQUES; THREAD SYNCHRONIZATIONS;

COMPLEXATION; COMPUTER ARCHITECTURE; DESIGN; FLOW INTERACTIONS; LEARNING SYSTEMS; MICROPROCESSOR CHIPS; STATISTICAL METHODS; STATISTICS;

ARCHITECTURAL DESIGN;

EID: 56449115895     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IISWC.2008.4636101     Document Type: Conference Paper

References (24)

1. D. A. Penry, D. Fay, D. Hodgdon, R.Wells, G. Schelle, D. I. August and D. Connors, Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors, HPCA, 2006.
2. L. Eeckhout, R. Bell Jr., B. Stougie, K. De Bosschere, and L. John, Improved Control Flow in Statistical Simulation for Accurate and Efficient Processor Design Studies, ISCA, 2004.
3. R. H. Bell, Jr. and L. K. John, Improved Automatic Testcase Synthesis for Performance Model Validation, ICS, 2005.
4. C. Hsieh and M. Pedram, Microprocessor Power Estimation using Profile-driven Program Synthesis, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 17(11), pp. 1080-1089, 1998.
5. A. Joshi, L. Eeckhout, R. H.Bell Jr., and L. K. John Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks, ISWC, 2006.
6. R. H. Bell, Jr., L. Eeckhout, L. K. John and K. De Bosschere, Deconstructing and Improving Statistical Simulation in HLS, Workshop on Debunking, Duplicating, and Deconstructing, 2004.
7. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. Janapareddi, and K. Hazelwood, Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation, PLDI, 2005.
8. A. Alameldeen, et al., Evaluating Non-deterministic Multi-threaded Commercial Workloads, Proceedings of the Computer Architecture Evaluation using Commercial Workloads, 2002.
9. Boost C++ Libraries. http://www.boost.org/
10. D. Genbrugge, L. Eeckhout, K. De Bosschere, Accurate Memory Data Flow Modeling in Statistical Simulation, ICS, 2006.
11. S. Nussbaum, S. and J. E. Smith, Statistical Simulation of Symmetric Multiprocessor Systems, Annual Simulation Symposium, 2002.
12. I. Daubechies, Ten Lectures on Wavelets, Capital City Press, Montpelier, Vermont, 1992.
13. T. Sherwood, E. Perelman, G. Hamerly and B. Calder, Automatically Characterizing Large Scale Program Behavior, ASPLOS, 2002.
14. R. E. Wunderlich, T. F. Wenisch, B. Falsafi and J. C. Hoe, SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling, ISCA, 2003.
15. M. V. Biesbrouck, L. Eeckhout, and B. Calder, Considering All Starting Points for Simultaneous Multi-threading Simulation, ISPASS, 2006.
16. S. Nussbaum and J.E. Smith, Modeling Superscalar Processors via Statistical Simulation, PACT, 2001.
17. L. Eeckhout and K. De Bosschere, Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces, PACT, 2001.
18. L. Eeckhout, S. Nussbaum, J. E. Smith, and K. De Bosschere, Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox, IEEE Micro, 23(5):26-38, 2003.
19. D. Genbrugge and L. Eeckhout, Statistical Simulation of Chip Multiprocessors Running Multi-Program Workloads, ICCD, 2007.
20. A. Joshi, J. J. Yi, R. H. Bell Jr., L. Eeckhout, L. K. John, and D. J. Lilja, Evaluating the Efficacy of Statistical Simulation for Design Space Exploration, ISPASS, 2006
21. M. Oskin, F. Chong, M. Farrens, HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Design, ISCA, 2000.
22. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh and A. Gupta, The SPLASH-2 Programs: Characterization and Methodological Considerations, ISCA, 1995.
23. VTune. http://www.intel.com/software/products/vtune/
24. D. Chiou, D. Sunwoo, J. Kim, N. Patil, W. Reinhart, E. Johnson, J. Keefe, and H. Angepat, FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators, MICRO, December 2007.