-
1
-
-
33750380212
-
Understanding the iimpact of x86/nt computing on microarchitecture
-
Chapter 10. Kluwer Academic Publishers
-
R. Bhargava, J. Rubio, S. Kannan, L. K. John, D. Christie, and L. Klaes. Understanding the iimpact of x86/nt computing on microarchitecture. In Chapter 10. Workload characterization of emerging computer applications. Kluwer Academic Publishers, 2001.
-
(2001)
Workload Characterization of Emerging Computer Applications
-
-
Bhargava, R.1
Rubio, J.2
Kannan, S.3
John, L.K.4
Christie, D.5
Klaes, L.6
-
3
-
-
12844286028
-
Application-level checkpointing for shared memory programs
-
G. Bronevetsky, D. Marques, K. Pingali, P. Szwed, and M. Schulz. Application-level checkpointing for shared memory programs. In Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 235-247, 2004.
-
(2004)
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems
, pp. 235-247
-
-
Bronevetsky, G.1
Marques, D.2
Pingali, K.3
Szwed, P.4
Schulz, M.5
-
4
-
-
0003465202
-
-
Technical Report CS-TR-U7-1342, University of Wisconsin, Madison, June
-
D. C. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report CS-TR-U7-1342, University of Wisconsin, Madison, June 1997.
-
(1997)
The SimpleScalar Tool Set, Version 2.0
-
-
Burger, D.C.1
Austin, T.M.2
-
6
-
-
12344302477
-
-
The Transaction Processing Performance Council. Dec
-
The Transaction Processing Performance Council. Tpc benchmark c: Standard specification. http://www.tpc.org/tpcc/spec/tpcc current.pdf, Dec 2003.
-
(2003)
Tpc Benchmark C: Standard Specification
-
-
-
7
-
-
0036470119
-
Asim: A performance model framework
-
J. Emer, P. Ahuja, E. Borch, A. Klauser, C.K. Luk, S. Manne, S. S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan. Asim: A performance model framework. Computer, 35(2):68-76, 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 68-76
-
-
Emer, J.1
Ahuja, P.2
Borch, E.3
Klauser, A.4
Luk, C.K.5
Manne, S.6
Mukherjee, S.S.7
Patil, H.8
Wallace, S.9
Binkert, N.10
Espasa, R.11
Juan, T.12
-
8
-
-
33744474064
-
The strong correlation between code signatures and performance
-
March
-
J. Lau, J. Sampson, E. Perelman, G. Hamerly, and B. Calder. The strong correlation between code signatures and performance. In ISPASS, March 2005.
-
(2005)
ISPASS
-
-
Lau, J.1
Sampson, J.2
Perelman, E.3
Hamerly, G.4
Calder, B.5
-
9
-
-
31944440969
-
Pin: Building customized program analysis tools with dynamic instrumentation
-
Chicago, IL, June
-
C. K Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: Building customized program analysis tools with dynamic instrumentation. In Programming Language Design and Implementation, Chicago, IL, June 2005.
-
(2005)
Programming Language Design and Implementation
-
-
Luk, C.K.1
Cohn, R.2
Muth, R.3
Patil, H.4
Klauser, A.5
Lowney, G.6
Wallace, S.7
Reddi, V.J.8
Hazelwood, K.9
-
10
-
-
0036469676
-
Simics: A full system simulation platform
-
P. S. Magnnsson, M. Christensson, J. Eskilson, D. Forsgren, G. Hllberg, J. Hgberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. Computer, 35(2):50-58, 2002.
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 50-58
-
-
Magnnsson, P.S.1
Christensson, M.2
Eskilson, J.3
Forsgren, D.4
Hllberg, G.5
Hgberg, J.6
Larsson, F.7
Moestedt, A.8
Werner, B.9
-
11
-
-
0036040311
-
Full-system timing-first simulation
-
C. J. Mauer, M. D. Hill, and D. A. Wood. Full-system timing-first simulation. SIGMETRICS Perform. Eval. Rev., 30(1):108-116, 2002.
-
(2002)
SIGMETRICS Perform. Eval. Rev.
, vol.30
, Issue.1
, pp. 108-116
-
-
Mauer, C.J.1
Hill, M.D.2
Wood, D.A.3
-
12
-
-
27544515395
-
Bugnet: Continuously recording program execution for deterministic replay debugging
-
June
-
S. Narayanasamy, G. Pokarn, and B. Calder. Bugnet: Continuously recording program execution for deterministic replay debugging. In ISCA, June 2005.
-
(2005)
ISCA
-
-
Narayanasamy, S.1
Pokarn, G.2
Calder, B.3
-
13
-
-
21644454187
-
Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation
-
December
-
H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi. Pinpointing representative portions of large Intel Itanium programs with dynamic instrumentation. In MICRO-37, December 2004.
-
(2004)
MICRO-37
-
-
Patil, H.1
Cohn, R.2
Charney, M.3
Kapoor, R.4
Sun, A.5
Karunanidhi, A.6
-
14
-
-
33744471950
-
Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification
-
March
-
J. Ringenberg, C. Pelosi, D. Oehmke, and T. Mudge. Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification. In ISPASS'05, March 2005.
-
(2005)
ISPASS'05
-
-
Ringenberg, J.1
Pelosi, C.2
Oehmke, D.3
Mudge, T.4
-
15
-
-
0030653560
-
Using the simos machine simulator to study complex computer systems
-
M. Rosenblum, E. Bugnion, S. Devine, and S. A. Herrod. Using the simos machine simulator to study complex computer systems. Modeling and Computer Simulation, 7(1):78-103, 1997.
-
(1997)
Modeling and Computer Simulation
, vol.7
, Issue.1
, pp. 78-103
-
-
Rosenblum, M.1
Bugnion, E.2
Devine, S.3
Herrod, S.A.4
-
17
-
-
28744440545
-
Performance analysis and validation of the intel pentium 4 processor on 90nm technology
-
February
-
R. Singhal, K.S. Venkatraman, E. Cohn, J.G. Holm, D. Koufaty, M.J. Lin, M. Madhav, M. Mattwandel, N. Nidhi, J. Pearce, and M. Seshadri. Performance) analysis and validation of the intel pentium 4 processor on 90nm technology. In Intel Technology Journal, February 2004.
-
(2004)
Intel Technology Journal
-
-
Singhal, R.1
Venkatraman, K.S.2
Cohn, E.3
Holm, J.G.4
Koufaty, D.5
Lin, M.J.6
Madhav, M.7
Mattwandel, M.8
Nidhi, N.9
Pearce, J.10
Seshadri, M.11
-
18
-
-
4544385770
-
Simsnap: Fast-forwarding via native execution and application-level checkpointing
-
February
-
P.K. Szwed, D. Marques, R.M. Buels, S.A. McKee, and M. Schulz. Simsnap: Fast-forwarding via native execution and application-level checkpointing. In Proc. HPCA 2004 Interact-8: Workshop on the Interaction between Compilers and Computer Architectures, February 2004.
-
(2004)
Proc. HPCA 2004 Interact-8: Workshop on the Interaction between Compilers and Computer Architectures
-
-
Szwed, P.K.1
Marques, D.2
Buels, R.M.3
McKee, S.A.4
Schulz, M.5
-
19
-
-
0029666641
-
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
-
D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In ISCA, pages 191-202, 1996.
-
(1996)
ISCA
, pp. 191-202
-
-
Tullsen, D.M.1
Eggers, S.J.2
Emer, J.S.3
Levy, H.M.4
Lo, J.L.5
Stamm, R.L.6
-
20
-
-
0003335469
-
Softsdv: A pre-silicon software development environment for the ia-64 architecture
-
December
-
R. Uhlig, R. Fishtein, O. Gershon, I. Hirsh, and H. Wang. Softsdv: A pre-silicon software development environment for the ia-64 architecture. In Intel Technology Journal, December 1999.
-
(1999)
Intel Technology Journal
-
-
Uhlig, R.1
Fishtein, R.2
Gershon, O.3
Hirsh, I.4
Wang, H.5
-
21
-
-
0038346244
-
SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
-
June
-
Roland E. Wunderlich, Thomas F Wenisch, Babak Falsafi, and James C. Hoe. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In ISCA-30, June 2003.
-
(2003)
ISCA-30
-
-
Wunderlich, R.E.1
Wenisch, T.F.2
Falsafi, B.3
Hoe, J.C.4
-
22
-
-
28444474809
-
Characterizing and comparing prevailing simulation techniques
-
February
-
J. J. Yi, S. V. Kodakara, R. Sendag, D. J. Lilja, and D. M. Hawkins. Characterizing and comparing prevailing simulation techniques. In HPCA-11, February 2005.
-
(2005)
HPCA-11
-
-
Yi, J.J.1
Kodakara, S.V.2
Sendag, R.3
Lilja, D.J.4
Hawkins, D.M.5
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