The optimum pipeline depth for a microprocessor

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 7-13

  Hartstein, A ^a   Puzak, Thomas R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATABASE SYSTEMS; JAVA PROGRAMMING LANGUAGE; ONLINE SYSTEMS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PROGRAM ASSEMBLERS; WEBSITES;

ON-LINE TRANSACTION PROCESSING (OLTP); OPTIMAL PIPELINE DEPTHS;

MICROPROCESSOR CHIPS;

EID: 0036296817     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Optimal pipelining in supercomputers
2. Clock rate versus IPC: The end of the road for conventional microarchitectures
3. Characterization of branch and data dependencies in programs for evaluating pipeline performance
4. Instruction-level program and processor modeling
5. Simulation and analysis of a pipeline processor
6. Contrasting characteristics and cache performance of technical and multi-user commercial workloads
7. Prefetching and memory system behavior of the SPEC95 benchmark suite