A statistically rigorous approach for improving simulation methodology

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 281-291

  Yi, J J ^a   Lilja, D J ^a   Hawkins, D M ^b  

^a University of Minnesota   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Analytical models; Application software; Computational modeling; Computer architecture; Computer simulation; Costs; Performance analysis; Space exploration; Statistical analysis; Time factors

Indexed keywords

ANALYTICAL MODELS; APPLICATION PROGRAMS; BENCHMARKING; COMPUTER SIMULATION; COMPUTER SOFTWARE; COST BENEFIT ANALYSIS; COSTS; INTEGRATED CIRCUIT DESIGN; SPACE RESEARCH; STATISTICAL METHODS; STATISTICS; SUPERCOMPUTERS;

COMPUTATIONAL MODEL; PERFORMANCE ANALYSIS; PROCESSOR ARCHITECTURES; PROCESSOR PERFORMANCE; SIMULATION METHODOLOGY; SPACE EXPLORATIONS; STATISTICAL TECHNIQUES; TIME FACTORS;

COMPUTER ARCHITECTURE;

EID: 33749057743     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183546     Document Type: Conference Paper

References (33)

1. P. Bannon and Y. Saito, "The Alpha 21164PC Microprocessor", International Computer Conference, 1997.
2. B. Black and J. Shen, "Calibration of Microprocessor Performance Models", IEEE Computer, Vol. 31, No. 5, May 1998, Pages 59-65.
3. D. Burger and T. Austin, "The SimpleScalar Tool Set, Version 2. 0", University of Wisconsin-Madison Computer Sciences Department Technical Report #1342, 1997.
4. H. Cain, K. Lepak, B. Schwartz, M. Lipasti, "Precise and Accurate Processor Simulation", Workshop on Computer Architecture Evaluation using Commercial Workloads, 2002.
5. R. Desikan, D. Burger, S. Keckler, "Measuring Experimental Error in Microprocessor Simulation", International Symposium on Computer Architecture, 2001.
6. J. Edmondson, P. Rubinfeld, R. Preston, "Superscalar Instruction Execution in the 21164 Alpha Microprocessor", IEEE Micro, Vol. 15, No. 2, March-April 1995, Pages 33-43.
7. L. Eeckhout, H. Vandierendonck, K. De Bosschere, "Workload Design: Selecting Representative Program-Input Pairs"; International Conference on Parallel Architectures and Compilations Techniques, 2002.
8. J. Gibson, R. Kunz, D. Ofelt, M. Horowitz, J. Hennessy, M. Heinrich, "FLASH vs. (Simulated) FLASH: Closing the Simulation Loop", International Conference on Architectural Support for Programming Languages and Operating Systems, 2000.
9. R. Giladi and N. Ahituv, "SPEC as a Performance Evaluation Measure", IEEE Computer, Vol. 28, No. 8, August 1995, Pages 33-42.
10. R. Glamm and D. Lilja, "Automatic Verification of Instruction Set Simulation Using Synchronized State Comparison", Annual Simulation Symposium, 2001.
11. T. Horel and G. Lauterbach, "UltraSPARC-III: Designing Third-Generation 64-Bit Performance", IEEE Micro, Vol. 19, No. 3, May-June 1999, Pages 73-85.
12. R. Kessler, E. McLellan, D. Webb, "The Alpha 21264 Microprocessor Architecture", International Conference on Computer Design, 1998.
13. R. Kessler, "The Alpha 21264 Microprocessor", IEEE Micro, Vol. 19, No. 2, March-April 1999, Pages 24-36.
14. A. KleinOsowski and D. J. Lilja, "MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research", Vol. 1, June 2002.
15. A. Kumar, "The HP PA-8000 RISC CPU", IEEE Micro, Vol. 17, No. 2, March-April 1997, Pages 27-32
16. D. Leiholz and R. Razdan, "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor", International Computer Conference, 1997.
17. D. Lilja, "Measuring Computer Performance", Cambridge University Press, 2000.
18. M. Matson, D. Bailey, S. Bell, L. Biro, S. Butler, J. Clouser, J. Farrell, M. Gowan, D. Priore, K. Wilcox, "Circuit Implementation of a 600 MHz Superscalar RISC Microprocessor", International Conference on Computer Design, 1998.
19. D. C. Montgomery, "Design and Analysis of Experiments", Third Edition, Wiley 1991.
20. D. Noonburg and J. Shen, "A Framework for Statistical Modeling of Superscalar Processor Performance ", International Symposium on High Performance Computer Architecture, 1997.
21. K. Normoyle, M. Csoppenszky, A. Tzeng, T. Johnson, C. Furman, J. Mostoufi, "UltraSPARC-IIi: Expanding the Boundaries of a System on a Chip", IEEE Micro, Vol. 18, No. 2, March-April 1998, Pages 14-24.
22. M. Oskin, F. Chong, M. Farrens, "HLS: Combining Statistical and Symbolic Simulation to Guide Microprocessor Designs", International Symposium on Computer Architecture, 2000.
23. R. Plackett and J. Burman, "The Design of Optimum Multifactorial Experiments", Biometrika, Vol. 33, Issue 4, June 1956, Pages 305-325.
24. J. Silc, B. Robic, T. Ungerer, "Processor Architecture: From Dataflow to Superscalar and Beyond", Springer-Verlag, 1999.
25. D. Sima, T. Fountain, P. Kacsuk, "Advanced Computer Architectures, A Design Space Approach", Addison Wesley Longman, 1997.
26. K. Skadron, P. Ahuja, M. Martonosi, D. Clark, "Branch Prediction, Instruction-Window Size, Cache Size: Performance Trade-Offs and Simulation Techniques", IEEE Transactions on Computers, Vol. 48, No. 11, November 1999, Pages 1260-1281.
27. A. Sodani and G. Sohi, "Dynamic Instruction Reuse", International Symposium on Computer Architecture, 1997.
28. S. Song, M. Denman, J. Chang, "The PowerPC 604 RISC Microprocessor", IEEE Micro, Vol. 14, No. 5, October 1994, Pages 8-17.
29. M. Tremblay and J. M. O'Connor, "UltraSparc I: A Four-Issue Processor Supporting Multimedia", IEEE Micro, Vol. 16, No. 2, March-April 1996, Pages 42-50.
30. K. Yeager, "The MIPS R10000 Superscalar Microprocessor", IEEE Micro, Vol. 16, No. 2, March-April 1996, Pages 28-40.
31. J. Yi, R. Sendag, D. Lilja, "Increasing Instruction-Level Parallelism with Instruction Precomputation", Euro-Par 2002.
32. J. Yi and D. Lilja, "Effects of Processor Parameter Selection on Simulation Results", MSI Report 2002/146, 2002.
33. J. Yi, D. Lilja, D. Hawkins, "A Statistically Rigorous Approach for Improving Simulation Methodology", ARCTiC Technical Report 02-07, 2002.