Computer-aided design for low-power robust computing in nanoscale CMOS

Proceedings of the IEEE

Volumn 95, Issue 3, 2007, Pages 507-529

  Sylvester, Dennis ^a   Srivastava, Ashish ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

CMOS; Integrated circuits; Low power; Parametric yield

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; LOW POWER ELECTRONICS; SAMPLING; VLSI CIRCUITS; VOLTAGE SCALING;

DESIGN ROBUSTNESS; JOINT OPTIMIZATION; LOW POWER; MULTIOBJECTIVE FUNCTION OPTIMIZATION; PARAMETRIC YIELD; PERFORMANCE METRICS; POWER REDUCTION TECHNIQUES; STATISTICAL OPTIMIZATION;

COMPUTER AIDED DESIGN;

EID: 50249093216     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.889370     Document Type: Article

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