Efficient and accurate gate sizing with piecewise convex delay models

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 807-812

  Tennakoon, Hiran ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

Delay modeling; Gate sizing; Lagrangian relaxation; Optimization; Piecewise convex

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; LAGRANGE MULTIPLIERS; MATHEMATICAL MODELS;

DELAY MODELING; GATE SIZING; LAGRANGIAN RELAXATION; PIECEWISE CONVEX;

GATES (TRANSISTOR);

EID: 27944445067     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193926     Document Type: Conference Paper

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