Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 783-787

  Srivastava, Ashish ^a   Sylvester, Dennis ^a   Blaauw, David ^a  

^a University of Michigan   (United States)

Author keywords

Multiple voltages; Optimization; Power dissipation

Indexed keywords

ALGORITHMS; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; EXTRAPOLATION; OPTIMIZATION; SENSITIVITY ANALYSIS; THRESHOLD VOLTAGE;

CLUSTERED VOLTAGE SCALING (CVS); DUAL-VDD DESIGNS; MULTIPLE VOLTAGES; POWER DISSIPATION;

ELECTRIC LOSSES;

EID: 4444327756     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996777     Document Type: Conference Paper

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