On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 5, 2001, Pages 616-629

  Chen, Chunhong ^a,b   Srivastava, Ankur ^a,c   Sarrafzadeh, Majid ^a,c  

^a IEEE   (Canada)

^b UNIVERSITY OF WINDSOR   (Canada)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Dual supply voltages; Gate level; Maximal weighted independent set; Power optimization; Timing constraints

Indexed keywords

POWER OPTIMIZATION;

ALGORITHMS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; HEURISTIC METHODS; LOGIC GATES; OPTIMIZATION; TIME MEASUREMENT;

CMOS INTEGRATED CIRCUITS;

EID: 0035472548     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.953496     Document Type: Article

References (27)

1. Low-power CMOS digital design
2. Cluster voltage scaling technique for low-power design
3. A low power design method using multiple supply voltages
4. Variable voltage scheduling
5. Automated low power technique exploiting multiple supply voltage applied to a media processor
6. A linear time heuristic for improving network partitions
7. 1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS
8. Generation of performance constraints for layout
9. Scheduling with multiple voltages
10. Energy minimization using multiple supply voltages
11. Maximum independent sets on transitive graphs and their applications in testing and CAD
12. Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques
13. Layout techniques supporting the use of dual supply voltages for cell-based designs
14. Power reduction by simultaneous voltage scaling and gate sizing
15. Gate-level design exploiting dual supply voltages for power-driven applications
16. Synthesis of low power CMOS VLSI circuits using dual supply voltages
17. Design and optimization of dual-threshold circuits for low-voltage low-power applications
18. Provably good algorithm for low power consumption with dual supply voltages
19. An effective algorithm for gate-level power-delay tradeoff using two voltages
20. Toward a high level power estimation capability
21. Multilevel hypergraph partitioning: Applications in VLSI design
22. Scheduling with multiple voltages under resource constraints
23. Power optimization issues in dual voltage design
24. Power optimization of delay constrained circuits