Microarchitecture-aware floorplanning using a statistical design of experiments approach

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 579-584

  Nookala, Vidyasagar ^a   Chen, Ying ^a   Lilja, David J ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

Floorplanning; Microarchitecture; Wire pipelining

Indexed keywords

CLOCKS; FLIP FLOP CIRCUITS; STATISTICS;

FLOORPLANNING; MULTI-CYCLE DELAYS; STATISTICAL DESIGN;

MICROPROCESSOR CHIPS;

EID: 27944502073     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193877     Document Type: Conference Paper

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