Linear programming for sizing, Vth and Vdd assignment

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 149-154

  Chinnery, D G ^a   Keutzer, K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Delay; Linear program; Power; Sizing

Indexed keywords

COMPUTER SOFTWARE; ELECTRIC NETWORK ANALYSIS; GATES (TRANSISTOR); POWER ELECTRONICS; PROBLEM SOLVING;

DELAY; LINEAR PROGRAM; POWER; SIZING;

LINEAR PROGRAMMING;

EID: 28444487522     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1077603.1077642     Document Type: Conference Paper

References (9)

1. th, Integrated Circuits," IEEE International Symposium on System-on-Chip, 2003, pp. 151-154.
2. Fishburn, J.P., and Dunlop, A.E., "TILOS: A Posynomial Programming Approach to Transistor Sizing," International Conference on Computer-Aided Design, 1985, pp. 326-328.
3. Forrest, J., Nuez, D., and Lougee-Heimer, R., CLP User Guide, http://www.coin-or.org/Clp/userguide/
4. K. Kasamsetty, M. Ketkar and S. S. Sapatnekar, "A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 7, 2000, pp. 779-788.
5. Kulkarni, S., and Sylvester, D., "Fast and Energy-Efficient Asynchronous Level Converters for Multi-VDD Design," IEEE Transactions on VLSI Systems, Sept. 2004, pp. 926-936.
6. Kulkarni, S., Srivastava, A., and Sylvester, D., "A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems," IEEE/ACM International Symposium on Low-Power Electronics Design, 2004, pp. 200-205.
7. Nguyen, D., et al., "Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization," International Symposium on Low Power Electronics and Design, 2003, pp. 158-163.
8. Srivastava, A., Sylvester, D., and Blaauw, D., "Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design," IEEE/ACM Design, Automation and Test Conf., Paris, France, 2004, pp. 718-719.
9. Tennakoon, H., and Sechen, C., "Gate Sizing Using Lagrangian Relaxation Combined with a Fast Gradient-Based Pre-Processing Step," International Conference on Computer-Aided Design, 2002, pp. 395-402.