Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 395-402

  Tennakoon, Hiran ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST GRADIENT-BASED PRE-PROCESSING STEP; GATE SIZING; LAGRANGIAN RELAXATION;

ALGORITHMS; CONSTRAINT THEORY; EQUIVALENT CIRCUITS; GRADIENT METHODS;

LAGRANGE MULTIPLIERS;

EID: 0036911571     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774631     Document Type: Conference Paper

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