Algorithms for minimizing standby power in deep submicrometer, dual - V t CMOS circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 3, 2002, Pages 306-318

  Wang, Qi ^a,b   Vrudhula, Sarma B K ^a,c  

^a IEEE   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c University of Arizona   (United States)

Author keywords

CMOS; Dual threshold voltage; Low power CMOS; Subthreshold current

Indexed keywords

DEEP SUBMICROMETER; DUAL THRESHOLD VOLTAGE; POWER DISSIPATION; STANDBY POWER; SUBTHRESHOLD CURRENT;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENT CONTROL; MICROELECTRONIC PROCESSING; POWER CONTROL; THRESHOLD VOLTAGE; TRANSISTORS; VOLTAGE CONTROL;

COMPUTER AIDED NETWORK ANALYSIS;

EID: 0036494388     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.986424     Document Type: Article

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