Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 14-19

  Meijer, Maurice ^a   Pessolano, Francesco ^a   De Gyvez, José Pineda ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Adaptive body bias; Adaptive voltage scaling; CMOS; Leakage; Low power; Performance optimization

Indexed keywords

LEAKAGE CURRENTS; LOGIC GATES; OPTIMIZATION; OSCILLATORS (ELECTRONIC); TEMPERATURE CONTROL; THRESHOLD VOLTAGE; TRANSISTORS;

ADAPTIVE BODY BIAS (ABB); ADAPTIVE VOLTAGE SCALING (AVS); LOW POWER; PERFORMANCE OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 16244408629     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013245     Document Type: Conference Paper

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