MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 495-500

  Kao, James ^a   Narendra, Siva ^a   Chandrakasan, Anantha ^a  

^a USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER ELECTRONICS; SLEEP RESEARCH; TRANSISTORS; ALGORITHMS; COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC DISCHARGES; GATES (TRANSISTOR);

DELAY CHARACTERISTICS; DISCHARGE PATTERNS; LOW-POWER OPERATION; MODULE-BASED; MULTI-THRESHOLD CMOS; PERFORMANCE CONSTRAINTS; SLEEP TRANSISTORS; UPPER BOUND;

CMOS INTEGRATED CIRCUITS;

SLEEP TRANSISTORS;

EID: 0031639695     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277180     Document Type: Conference Paper

References (8)

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8. N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design, " Addison-Wesley, Reading MA., pp. 554-557, 1993.