Static leakage reduction through simultaneous vt/TOX and state assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 7, 2005, Pages 1014-1029

  Lee, Dongwoo ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Dual oxide thickness; Dual threshold voltage; Gate leakage; Leakage currents; Power optimization; State assignment; Subthreshold leakage

Indexed keywords

BENCHMARKING; ELECTRIC BATTERIES; GRAPH THEORY; LOGIC GATES; OPTIMIZATION; STATE ASSIGNMENT; THRESHOLD VOLTAGE; TRANSISTORS;

DUAL OXIDE THICKNESS; DUAL THRESHOLD VOLTAGE; GATE LEAKAGE; POWER OPTIMIZATION; SUBTHRESHOLD LEAKAGE;

LEAKAGE CURRENTS;

EID: 22544460501     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.847906     Document Type: Article

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