Analysis of pulse signaling for low-power on-chip global bus design

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 401-406

  Chen, Min ^a   Cao, Yu ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN METRICS; DEVELOPED MODEL; DYNAMIC POWER CONSUMPTION; MODEL ACCURACY; PROPAGATION LENGTHS; PULSE PROPAGATION; PULSE SIGNALING; SPICE SIMULATIONS;

BUSES; COMPUTER SIMULATION; ELECTRIC PROPERTIES; SIGNALING;

DESIGN;

EID: 56749100060     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.27     Document Type: Conference Paper

References (11)

1. International Technology Roadmap for Semiconductors, 2004.
2. C. Hu, "CMOS for one more century?" IEEE CICC, Keynote Speech, 2004.
3. R. Bashirullah, et al., "A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage model signaling," IEEE VLSI Symp. on Circuits, pp. 392-392, 2004.
4. L. A. Hayden and V. K. Tripathi, "Pulse signaling using capacitively-coupled CMOS," IEEE EPEC, pp. 7-9, 1994.
5. J. Kim, et al., "A low power capacitive coupled bus interface based on pulsed signaling," IEEE CICC, pp. 35-38, 2004.
6. P. Wang, G. Pei, and E. C.-C. Kan, "Pulsed wave interconnect," IEEE TVLSI, vol. 12, no. 5, pp. 453-463, May 2004.
7. Y. Cao, et al., "New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation," IEEE CICC, pp. 201-204, 2000 (http://wwwdevice. eecs.berkeley.edu/~ptm).
8. X. Qi, et al., "On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation", IEEE CICC, pp. 487-490, 2000.
9. S. Wong, G. Lee, and D. Ma, "Modeling of interconnect capacitance, delay, and crosstalk in VLSI", IEEE TSM, vol. 13, no. 1, pp. 108-111, Feb. 2000.
10. Y. I. Ismail, E. G. Friedman, and Jose L.Neves, "Equivalent Elmore delay for RLC trees," DAC, pp. 715-720, June 1999.
11. A. B. Kahng, K. Masuko, and S. Muddu, "Analytical delay models for VLSI interconnects under ramp input," ICCAD, pp. 30-36, 1996.