Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 11, 2005, Pages 1225-1237

  Kaul, Himanshu ^a,b   Sylvester, Dennis ^a,c   Anders, Mark A ^a,b   Krishnamurthy, Ram K ^a,b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuit design; Encoding; Low power; On chip buses

Indexed keywords

CIRCUIT DESIGNS; ENCODING CIRCUITS; LOW POWER; ON CHIP BUSES;

BUSBARS; ELECTRIC NETWORK ANALYSIS; GAIN CONTROL; INTERCONNECTION NETWORKS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

INTEGRATED CIRCUIT LAYOUT;

EID: 33947118188     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859589     Document Type: Article

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