Modeling and analysis of leakage power considering within-die process variations

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 64-67

  Srivastava, Ashish ^a   Bai, Robert ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a University of Michigan   (United States)

Author keywords

Leakage current; Monte Carlo; Variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CONTROLLABILITY; MONTE CARLO METHODS; NAND CIRCUITS; THRESHOLD VOLTAGE;

DRAIN-INDUCED BARRIER LOWERING; LEAKAGE POWER;

LEAKAGE CURRENTS;

EID: 0036954781     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146711     Document Type: Conference Paper

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