Discrete Vt assignment and gate sizing using a self-snapping continuous formulation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 705-712

  Shah, Saumil ^a   Srivastava, Ashish ^a   Sharma, Dushyant ^a   Sylvester, Dennis ^a   Blaauw, David ^a   Zolotov, Vladimir ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DISCRETE TIME CONTROL SYSTEMS; HEURISTIC METHODS; PROBLEM SOLVING; THEOREM PROVING;

GATE SIZING; POWER SAVINGS;

GATES (TRANSISTOR);

EID: 33751404357     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560157     Document Type: Conference Paper

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