An exact gate assignment algorithm for tree circuits under rise and fall delays

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 451-457

  Oliveira, Arlindo L ^a   Murgai, Rajeev ^b  

^a Cadence Laboratories / INESC ID   (Portugal)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL OPTIMIZATION; COMPUTER AIDED DESIGN; DELAY CIRCUITS; DIRECTED GRAPHS; DYNAMIC PROGRAMMING; OPTIMIZATION; POLYNOMIAL APPROXIMATION; POLYNOMIALS; TOPOLOGY; TREES (MATHEMATICS); CAPACITANCE; COMPUTATIONAL COMPLEXITY;

ASSIGNMENT ALGORITHMS; ASSIGNMENT PROBLEMS; BENCH-MARK PROBLEMS; DIRECTED ACYCLIC GRAPH (DAG); DYNAMIC PROGRAMMING ALGORITHM; PERFORMANCE OPTIMIZATIONS; POLYNOMIAL EXACT ALGORITHMS; TRADITIONAL APPROACHES;

PROBLEM SOLVING; ELECTRIC NETWORK PARAMETERS;

EXACT GATE ASSIGNMENT ALGORITHM; TREE CIRCUITS;

EID: 0034483994     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896513     Document Type: Conference Paper

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