The scaling challenge: Can correct-by-construction design help?

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 51-58

  Saxena, Prashant ^a   Menezes, Noel ^a   Cocchini, Pasquale ^a   Kirkpatrick, Desmond A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Clocked Repeaters; Correct by construction Design; Design Fabrics; Interconnect; Logic Synthesis; Placement; Post RTL Design; Repeaters; Routing; Scaling; Technology Mapping

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FORMAL LOGIC; MICROPROCESSOR CHIPS;

LOGIC SYNTHESIS;

INTEGRATED CIRCUITS;

EID: 0037703176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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