Wave-pipelined on-chip global interconnect

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 127-132

  Zhang, Lizheng ^a   Hu, Yuhen ^a   Charlie, ^b   Chen, Chung Ping ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA COST; BIT RATES; CLOCK AND DATA RECOVERY; COMBINATIONAL LOGIC BLOCKS; DATA-COMMUNICATION; GLOBAL INTERCONNECTS; HIGH THROUGHPUT; LONG INTERCONNECT; MONTE CARLO SIMULATION; OFF-CHIP; ON CHIPS; ON-CHIP APPLICATIONS; PHASE LOCK LOOPS; REAL ESTATE; SERIAL LINK; SIGNAL PROPAGATION; TIMING CONSTRAINTS;

COMPUTER AIDED DESIGN; MONTE CARLO METHODS; TIMING CIRCUITS;

INTERCONNECTION NETWORKS;

EID: 84861421843     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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