First-order incremental block-based statistical timing analysis

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 331-336

  Visweswariah, C ^a   Ravindran, K ^b   Kalafala, K ^c   Walker, S G ^a   Narayan, S ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM MICROELECTRONICS   (United States)

Author keywords

Incremental; Statistical timing; Variability

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; AUTOMATION; COMPUTATIONAL METHODS; LOGIC GATES; NUMERICAL METHODS; PARAMETER ESTIMATION; PROBABILITY; PROBLEM SOLVING; ROBUSTNESS (CONTROL SYSTEMS);

CENTRAL PROCESSING UNIT (CPU); INCREMENTAL; STATISTICAL TIMING; VARIABILITY; VERIFICATION;

TIMING CIRCUITS;

EID: 4444233012     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996663     Document Type: Conference Paper

References (16)

1. C. Visweswariah, "Death, taxes and failing chips," Proc. 2003 Design Automation Conference, pp. 343-347, June 2003. Anaheim, CA.
2. R. P. Abato, A. D. Drumm, D. J. Hathaway, and L. P. P. P. van Ginneken, "Incremental timing analysis," U. S. Patent 5,508,937, April 1993.
3. J.-J. Liou, K.-T. Cheng, S. Kundu, and A. Krstic, "Fast statistical timing analysis by probabilistic event propagation," Proc. 2001 Design Automation Conference, pp. 661-666, June 2001. Las Vegas, NV.
4. M. R. C. M. Berkelaar, "Statistical delay calculation: a linear time method," Proc. TAU (ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems), December 1997.
5. A. B. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," Proc. 2003 Design Automation Conference, June 2003. Anaheim, CA.
6. L. Scheffer, "Explicit computation of performance as a function of process variation," Proc. TAU (ACM/IEEE workshop on timing issues in the specification and synthesis of digital systems), pp. 1-8, December 2002. Monterey, CA.
7. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," IEEE International Conference on Computer-Aided Design, pp. 621-625, November 2003. San Jose, CA.
8. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," IEEE International Conference on Computer-Aided Design, pp. 900-907, November 2003. San Jose, CA.
9. J. Jess, "Dfm in synthesis," research report, IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598, December 2001.
10. J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," Proc. 2003 Design Automation Conference, pp. 932-937, June 2003. Anaheim, CA.
11. C. E. Clark, "The greatest of a finite set of random variables," Operations Research, pp. 145-162, March-April 1961.
12. M. Cain, "The moment-generating function of the minimum of bivariate normal random variables," The American Statistician, vol. 48, pp. 124-125, May 1994.
13. C. Visweswariah, "System and method for statistical timing analysis of digital circuits," Docket YOR9-2003-401, August 2003. Filed with the U. S. Patent office.
14. C. Visweswariah, "System and method for probabilistic criticality prediction of digital circuits," Docket YOR9-2003-402, August 2003. Filed with the U.S. Patent office.
15. D. J. Hathaway, J. P. Alvarez, and K. P. Belkhale, "Network timing analysis method which eliminates timing variations between signals traversing a common circuit path," U. S. Patent 5,636,372, June 1997.
16. C. Visweswariah, "System and method for incremental statistical timing analysis of digital circuits," Docket YOR9-2003-403, August 2003. Filed with the U. S. Patent office.