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Volumn 1, Issue , 2005, Pages 399-404

Runtime leakage minimization through probability-aware dual-Vt or dual-Tox assignment

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ECONOMIC AND SOCIAL EFFECTS;

EID: 84860029267     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120884     Document Type: Conference Paper
Times cited : (8)

References (14)
  • 1
    • 33750599396 scopus 로고    scopus 로고
    • Leakage issues in IC design: Trends, estimation and avoidance
    • S. Narendra, et al., "Leakage issues in IC design: trends, estimation and avoidance", Proc. ICCAD (tutorial), 2003.
    • (2003) Proc. ICCAD (Tutorial)
    • Narendra, S.1
  • 2
    • 0001646635 scopus 로고
    • I-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • Aug.
    • S. Mutoh, et al., "I-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE JSSC, Aug. 1995.
    • (1995) IEEE JSSC
    • Mutoh, S.1
  • 3
    • 0031162017 scopus 로고    scopus 로고
    • A I-V high-speed MTCMOS circuit scheme for power-down application circuits
    • June
    • S. Shigematsu, et al., "A I-V high-speed MTCMOS circuit scheme for power-down application circuits," IEEE Journal of Solid-state Circuits, vol. 32, pp. 861-869, June 1997.
    • (1997) IEEE Journal of Solid-state Circuits , vol.32 , pp. 861-869
    • Shigematsu, S.1
  • 4
    • 0030712582 scopus 로고    scopus 로고
    • A gate-level leakage power reduction method for ultra-low-power CMOS circuits
    • J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proc. CICC, pp. 475-478, 1997.
    • (1997) Proc. CICC , pp. 475-478
    • Halter, J.1    Najm, F.2
  • 6
    • 0032680122 scopus 로고    scopus 로고
    • Models and algorithms for bounds on leakage in CMOS circuits
    • June
    • M.C. Johnson, et al., "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. CAD, pp. 714-725, June 1999.
    • (1999) IEEE Trans. CAD , pp. 714-725
    • Johnson, M.C.1
  • 7
    • 0031635596 scopus 로고    scopus 로고
    • Design and optimization of low voltage high performance dual threshold CMOS circuits
    • L. Wei, et al., "Design and optimization of low voltage high performance dual threshold CMOS circuits," Proc. DAC, 1998.
    • (1998) Proc. DAC
    • Wei, L.1
  • 8
    • 0036543067 scopus 로고    scopus 로고
    • Duet: An accurate leakage estimation and optimization tool for dual Vt circuits
    • April
    • S. Sirichotiyakul, er al., "Duet: an accurate leakage estimation and optimization tool for dual Vt circuits," IEEE Trans. VLSI, April 2002.
    • (2002) IEEE Trans. VLSI
    • Sirichotiyakul, S.1
  • 9
    • 0036907253 scopus 로고    scopus 로고
    • Standby power optimization via transistor sizing and dual threshold voltage assignment
    • M. Ketkar and S. Sapatnekar, "Standby power optimization via transistor sizing and dual threshold voltage assignment," Proc. ICCAD, 2002.
    • (2002) Proc. ICCAD
    • Ketkar, M.1    Sapatnekar, S.2
  • 10
    • 0042635859 scopus 로고    scopus 로고
    • Static leakage reduction through simultaneous threshold voltage and state assignment
    • D. Lee and D. Blaauw, "Static leakage reduction through simultaneous threshold voltage and state assignment," Proc. DAC, pp. 191-194, 2003.
    • (2003) Proc. DAC , pp. 191-194
    • Lee, D.1    Blaauw, D.2
  • 11
    • 0036056699 scopus 로고    scopus 로고
    • Life is CMOS: Why chase the life after?
    • G Sery, et al., "Life is CMOS: Why chase the life after?," Proc. DAC, pp.78-83, 2002.
    • (2002) Proc. DAC , pp. 78-83
    • Sery, G.1
  • 12
    • 84992255008 scopus 로고
    • Estimate of signal probability in combinational logic networks
    • S. Ercolani, et al., "Estimate of signal probability in combinational logic networks," Proc. European Test Conference, 1989, pp. 132 - 138.
    • (1989) Proc. European Test Conference , pp. 132-138
    • Ercolani, S.1
  • 14
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    • http://www.cbl.nesu.edu


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.