Minimizing total power by simultaneous Vdd/Vth assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 5, 2004, Pages 665-677

  Srivastava, Ashish ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Dual supply voltage; Level conversion; Power optimization

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; GATES (TRANSISTOR); OPTIMIZATION; THRESHOLD VOLTAGE;

DUAL SUPPLY VOLTAGE; LEVEL CONVERSION; MULTIVOLTAGE SYSTEMS; POWER OPTIMIZATION;

ELECTRIC POWER UTILIZATION;

EID: 2542494086     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.826551     Document Type: Article

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