Selective gate-length biasing for cost-effective runtime leakage control

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 327-330

  Gupta, Puneet ^a   Kahng, Andrew B ^a,b   Sharma, Puneet ^a   Sylvester, Dennis ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c University of Michigan   (United States)

Author keywords

Layout; Leakage; Lithography; Manufacturability; OPC; Power

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; LEAKAGE CURRENTS; LITHOGRAPHY; OPTIMIZATION; TERMINALS (ELECTRIC);

HIGH POWER DISSIPATION; MANUFACTURABILITY; OPC; POWER OPTIMIZATION;

GATES (TRANSISTOR);

EID: 4444245930     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996661     Document Type: Conference Paper

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