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Volumn , Issue , 2005, Pages 147-150

Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY CONTROL; VARIABLE-GATE VOLTAGE MTCMOS; WORST-CASE DELAY PENALTY;

EID: 30844463472     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (12)

References (11)
  • 1
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    • Nassif, S.R.1
  • 2
    • 84886705903 scopus 로고    scopus 로고
    • Parametric yield analysis and constrained-based supply voltage optimization
    • R. Rao, et al. "Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization," Proc. ISQED, 2005.
    • (2005) Proc. ISQED
    • Rao, R.1
  • 3
    • 2342583496 scopus 로고    scopus 로고
    • Controlling short-channel effects in deep-submicron SOI MOSFETS for improved reliability: A review
    • A. Chaudhry and M. J. Kumar. "Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETS for Improved Reliability: A Review," IEEE Trans. Device and Materials Reliability, pp 99-109, Vol. 4, No. 1, 2004.
    • (2004) IEEE Trans. Device and Materials Reliability , vol.4 , Issue.1 , pp. 99-109
    • Chaudhry, A.1    Kumar, M.J.2
  • 4
    • 84949480508 scopus 로고    scopus 로고
    • Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI
    • Y. Cao, et al. "Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI," Proc. ASIC/SOC, pp 411-415, 2002.
    • (2002) Proc. ASIC/SOC , pp. 411-415
    • Cao, Y.1
  • 5
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • S. Borkar. "Design Challenges of Technology Scaling," IEEE Micro, Vol. 19, No. 4, pp 23-29, 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 7
    • 0036954781 scopus 로고    scopus 로고
    • Modeling and analysis of leakage power considering within-die process variations
    • A. Srivastava, M. R. Bai, D. Sylvester, D. Blaauw. "Modeling and Analysis of Leakage Power Considering Within-Die Process Variations," Proc. ISLPED, pp 64-67, 2002.
    • (2002) Proc. ISLPED , pp. 64-67
    • Srivastava, A.1    Bai, M.R.2    Sylvester, D.3    Blaauw, D.4
  • 8
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variations and impact on circuits and microarchitecture
    • S. Borkar, et al. "Parameter Variations and Impact on Circuits and Microarchitecture," Proc. DAC, pp 338-342, 2003.
    • (2003) Proc. DAC , pp. 338-342
    • Borkar, S.1
  • 9
    • 4444351567 scopus 로고    scopus 로고
    • Parametric yield estimation considering leakage variability
    • R. Rao, A. Devgan, D. Blaauw, D. Sylvester. "Parametric Yield Estimation Considering Leakage Variability," Proc. DAC, pp 442-447, 2004.
    • (2004) Proc. DAC , pp. 442-447
    • Rao, R.1    Devgan, A.2    Blaauw, D.3    Sylvester, D.4
  • 10
    • 0029359285 scopus 로고
    • A 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
    • S. Mutoh, et al. "A 1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS," IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, 1995.
    • (1995) IEEE Journal of Solid-state Circuits , vol.30 , Issue.8
    • Mutoh, S.1
  • 11
    • 0036858210 scopus 로고    scopus 로고
    • Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
    • J. Tschanz, et al. "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, 2002.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , Issue.11
    • Tschanz, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.