High performance gate first HfSiON dielectric satisfying 45nm node requirements

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 425-428

  Quevedo Lopez, M A ^b   Krishnan, S A ^a   Kirsch, P D ^c   Li, H J ^d   Sim, J H ^a   Huffman, C ^b   Peterson, J J ^a   Lee, B H ^c   Pant, G ^e   Gnade, B E ^e   Kim, M J ^e   Wallace, R M ^e   Guo, D ^f   Bu, H ^f   Ma, T P ^f  

^a SEMATECH   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c IBM   (United States)

^d Infineon ^*

^e The University of Texas at Dallas   (United States)

^f Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HFSION; HIGH PERFORMANCE GATE;

CHARGE TRAPPING; CRYSTALLIZATION; DIELECTRIC FILMS; ELECTRON MOBILITY; HOLE MOBILITY;

GATE DIELECTRICS;

EID: 33847711402     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. P. Bai, et al., IEDM Tech. Dig., 657 (2004).
2. P. D. Kirsch, et al. EESDERC, p 367 (2005)
3. J. J. Peterson et al. Electrochem. Solid-State Lett., 7 (8) G164-G167 (2004)
4. A. Callegari et al. IEDM Tech. Dig., p825 (2004).
5. B.H.Lee et al., IEDM Tech. Dig., p.859 (2004).
6. E. P. Gusev et al, IEDM Tech. Dig., p.729 (2004).
7. H. R. Harris et al. Proceedings of IRPS, p.80 (2005).
8. R.Chau et al, EDL v.25, p.408 (2004).
9. G. Lucovsky, et al. J. Vac. Sci. Technol. A 18, 1163 (2000
10. M. A. Quevedo-Lopez et al. J. Appl. Phys. 97, 043508 (2005)
11. A. Shanware et al. IEDM Tech. Dig., p.38-6 (2003).
12. A. Shanware et al. IEDM Tech. Dig., p. 6 (2001).