Low-power on-chip communication based on transition-aware global signaling (TAGS)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 5, 2004, Pages 464-476

  Kaul, Himanshu ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Interconnect; Low power; Repeaters; Signaling

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ENERGY UTILIZATION; SIGNAL RECEIVERS; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION; TELECOMMUNICATION REPEATERS;

INTERCONNECTS; LOW POWERS; ON-CHIP SIGNALING; TRANSITION AWARE GLOBAL SIGNALING (TAGS);

CHIP SCALE PACKAGES;

EID: 2542421952     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.826199     Document Type: Article

References (25)

1. J. Cong et al., "Buffer block planning for interconnect-driven floorplanning," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1999, pp. 358-363.
2. J. D. Warnock et al., "The circuit and physical design of the POWER4 microprocessor," IBM J. Res. Develop., vol. 46, no. 1, pp. 53-76, 2002.
3. R. McInerny et al., "Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor," in Proc. Int. Symp. Physical Design (ISPD), 2000, pp. 99-104.
4. I. Dobbeleare et al., "Regenerative feedback repeaters for programmable interconnections," in Proc. Int. Solid State-Circuits Conf., 1995, pp. 116-117.
5. T. lima et al., "Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI," IEEE J. Solid-State Circuits, pp. 531-536, 1996.
6. A. Nalamalpu, S. Srinivasan, and W. Burlesson, "Boosters for driving long onchip interconnects - Design issues, interconnect synthesis, and comparison with repeaters," IEEE Trans. Computer-Aided Design of Circuits and Systems, vol. 21, pp. 50-62, Jan. 2002.
7. Y. Massoud et al., "Modeling and analysis of differential signaling for minimizing inductive crosstalk," in Proc. Design Automation Conf. (DAC), 2001, pp. 804-809.
8. R. M. Secareanu et al., "Exploiting hysteresis in a CMOS buffer," in Proc. Int. Conf. Electronics Circuits and Systems (ICECS), 1999, pp. 205-208.
9. H. Kaul and D. Sylvester, "Transition aware global signaling (TAGS)," in Proc. Int. Symp. Quality Electronic Design (ISQED), 2002, pp. 53-59.
10. (2002) Star-HSPICE - 2001.2. Synopsys, Inc.. [Online]. Available: http://www.synopsys.com/products/avmrg/hspice_ds.html
11. I. Sutherland et al., Logical Effort: Designing Fast CMOS Circuits. San Mateo, CA: Morgan Kauffman, 1999.
12. J. M. Rabaey et al., Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.
13. M. Kamon et al., "FastHenry: A multipole-accelerated 3-D inductance extraction program," IEEE Trans. Microwave Theory Tech., vol. 42, pp. 1750-1758, Sept. 1999.
14. R. Panda, Personal Communication. Austin, TX: Motorola, 2003.
15. (2002) Raphael RC2-2000.2. Synopsys, Inc.. [Online]. Available: http://www.synopsys.com/products/avmrg/raphael_ds.html
16. S. Morton, "On-chip signaling," presented at the Presented at Solid-State Circuits Conf. (ISSCC), San Francisco, CA, 2002.
17. (2000) ITRS. [Online]. Available: http://public.itrs.net
18. R. Krishnamurthy, "private communication," unpublished, 2003.
19. C. Alpert, Personal Communication. Austin, TX: IBM, 2003.
20. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison Wesley, 1990.
21. L. H. Chen et al., "Coping with buffer delay change due to power and ground noise," in Proc. Design Automation Conf. (DAC), 2002, pp. 860-865.
22. A. B. Kahng and S. Muddu, "An analytical delay model for RLC interconnects," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1507-1514, Dec. 1997.
23. S. D. Conte and C. de Boor, Elementary Numerical Analysis, 3rd ed. New York: McGraw-Hill, 1981.
24. D. Sylvester and K. Keutzer, "System-level performance modeling-with berkeley advanced chip performance calculator," in Proc. Int. Workshop Level Interconnect Prediction (SLIP), 1999, http://www-device.eecs.berkeley.edu/ ~dennis/bacpac/, pp. 109-114.
25. A. E. Caldwell et al., "GTX: The MARCO GSRC technology extrapolation system," in Proc. Design Automation Conf. (DAC), 2000, http://nexus6.cs.ucla.edu/GSRC/GTX/, pp. 693-698.