-
1
-
-
0031232922
-
Will physical scalability sabotage performance gains?
-
D. Matzke, "Will physical scalability sabotage performance gains?," Computer, vol. 30, pp. 37-39, 1997.
-
(1997)
Computer
, vol.30
, pp. 37-39
-
-
Matzke, D.1
-
3
-
-
0346778726
-
Full-chip interconnect power estimation and simulation considering concurrent repearter and flip-flop insertion
-
W. Liao and L. He, "Full-chip interconnect power estimation and simulation considering concurrent repearter and flip-flop insertion," in ICCAD, pp. 574-580, 2003.
-
(2003)
ICCAD
, pp. 574-580
-
-
Liao, W.1
He, L.2
-
4
-
-
0037322638
-
A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices
-
M. Rewienski and J. White, "A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices" IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 155-170, 2003.
-
(2003)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 155-170
-
-
Rewienski, M.1
White, J.2
-
6
-
-
0038346244
-
Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling
-
R. Wunderlich, T. Wenisch, B. Falsafi, and J. Hoe, "Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling," inInternational Symposium on Computer Architecture, pp. 84-95, 2003.
-
(2003)
International Symposium on Computer Architecture
, pp. 84-95
-
-
Wunderlich, R.1
Wenisch, T.2
Falsafi, B.3
Hoe, J.4
-
7
-
-
84862412068
-
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
-
UCLA EE Dept
-
C. Long, L. J. Simonson, W. Liao, and L. He, "Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects," tech. rep., UCLA EE Dept., http://eda.ee.ucla.edu/publications.html, 2004.
-
(2004)
Tech. Rep.
-
-
Long, C.1
Simonson, L.J.2
Liao, W.3
He, L.4
-
10
-
-
0030378255
-
VLSI module placement based on rectangle-packing by the sequence pair
-
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair, "IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1518-1524, 1996.
-
(1996)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 1518-1524
-
-
Murata, H.1
Fujiyoshi, K.2
Nakatake, S.3
Kajitani, Y.4
-
12
-
-
0027837680
-
Primal-dual rnc approximation algorithms for (multi)-set (multi)-cover and covering integer programs
-
S. Rajagopalan and V. Vazirani, "Primal-dual rnc approximation algorithms for (multi)-set (multi)-cover and covering integer programs," inFoundations of Computer Science, 1993. Proceedings., 34th Annual Symposium on, pp. 322-331, 1993.
-
(1993)
Foundations of Computer Science, 1993. Proceedings., 34th Annual Symposium on
, pp. 322-331
-
-
Rajagopalan, S.1
Vazirani, V.2
-
13
-
-
0016349356
-
Approximation algorithms for combinatorial problems
-
D. S. Johnson, "Approximation algorithms for combinatorial problems," J. Comput. Sys. Sci., vol. 9, pp. 256-278.
-
J. Comput. Sys. Sci.
, vol.9
, pp. 256-278
-
-
Johnson, D.S.1
-
14
-
-
0000203509
-
On the ratio of optimal integral and fractional covers
-
L. Lovasz, "On the ratio of optimal integral and fractional covers," Discrete Math., vol. 13, pp. 383-390.
-
Discrete Math.
, vol.13
, pp. 383-390
-
-
Lovasz, L.1
-
15
-
-
0043092230
-
Microarchitecture evaluation with physical planning
-
J. Cong, A. Jagannathan, G. Reinman, and M. Romesis, "Microarchitecture evaluation with physical planning," inProc. Design Automation Conf, pp. 32-35, 2003.
-
(2003)
Proc. Design Automation Conf
, pp. 32-35
-
-
Cong, J.1
Jagannathan, A.2
Reinman, G.3
Romesis, M.4
|