A new statistical optimization algorithm for gate sizing

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 272-277

  Mani, Murari ^a   Orshansky, Michael ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATE SIZING; POLYTOPE ALGORITHMS; STATISTICAL OPTIMIZATION ALGORITHMS; TIMING CONSTRAINTS;

BENCHMARKING; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; GATES (TRANSISTOR); OPTIMIZATION; VLSI CIRCUITS;

ALGORITHMS;

EID: 17644377645     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2004.1347933     Document Type: Conference Paper

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