Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

Semiconductor Science and Technology

Volumn 23, Issue 4, 2008, Pages

  Kranti, Abhinav ^a   Hao, Ying ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FILM THICKNESS; GATE DIELECTRICS; OPTIMIZATION; PLANAR WAVEGUIDES; POWER CONTROL; SILICON COMPOUNDS; STANDBY POWER SERVICE;

BACK GATE MISALIGNMENTS; LOW OPERATING POWER LOGICS; SILICON FILMS; SOI MOSFET DEVICES;

MOSFET DEVICES;

EID: 42449146100     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/23/4/045001     Document Type: Article

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