The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

Solid-State Electronics

Volumn 50, Issue 5, 2006, Pages 774-783

  Lim, Tao Chuan ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Cut off frequency; Doping gradient; Double gate SOI; Maximum oscillation frequency; Mixed Mode simulation; Spacers

Indexed keywords

DOPING (ADDITIVES); GATES (TRANSISTOR); OPTIMIZATION;

CUT OFF FREQUENCY; DOPING GRADIENT; DOUBLE GATE SOI; MAXIMUM OSCILLATION FREQUENCY; MIXED MODE SIMULATION; SPACERS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 33744946793     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.04.010     Document Type: Article

References (30)

1. Ernst T., Cristoloveanu S., Ghibaudo G., Ouisse T., Horiguchi S., Ono Y., et al. Ultimately thin double-gate SOI MOSFETs. IEEE Trans Electron Dev 50 (2003) 830-838
2. Kilchytska V., Neve A., Vancaillie L., Levacq D., Adriaensen S., van Meer H., et al. Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans Electron Dev 50 (2003) 577-588
3. Chen Q., Agrawal B., and Meindl J.D. A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs. IEEE Trans Electron Dev 49 (2002) 1086-1090
4. Jankovic N.D., and Armstrong G.A. Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers. Microelectron J 35 8 (2004) 647-653
5. Lim T.C., and Armstrong G.A. Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors. Solid-State Electron 49 6 (2005) 1034-1043
6. Doris B, Ieong M, Zhu T, Zhang Y, Steen M, Natzle W, et al., Newport M, Dobuzinsky D, Deshpande S, Petrus J, Jammy R, Haensch W. Device design considerations for ultra-thin SOI MOSFETs. In: IEEE International Electron Devices Meeting 2003. p. 27.3.1-4.
7. Fenouillet-Beranger C., Skotnicki T., Monfray S., Carriere N., and Boeuf F. Requirements for ultra-thin-film devices and new materials for the CMOS roadmap. Solid-State Electron 48 6 (2004) 961-967
8. Fossum JG, Chowdhury MM, Trivedi VP, King TJ, Choi YK, An J, et al. Physical insights on design and modeling of nanoscale FinFETs. In: IEEE International Electron Devices Meeting December 8-10 2003. p. 679-82.
9. Fossum JG, Wang LQ, Yang JW, Kim SH, Trivedi VP, Pragmatic design of nanoscale multi-gate CMOS. In: IEEE International Electron Devices Meeting 2004. p. 613-6.
10. Shang H., and White M.H. An ultra-thin midgap gate FDSOI MOSFET. Solid-State Electron 44 9 (2000) 1621-1625
11. International Technology Road Maps for Semiconductor 2003 edition. Available from: http://public.itrs.net.
12. Kedzierski J., Ieong M., Nowak E., Kanarsky T.S., Zhang Y., Roy R., et al. Extension and source/drain design for high-performance FinFET devices. IEEE Trans Electron Dev 50 (2003) 952-958
13. Chen Q., Harrell II E.M., and Meindl J.D. A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Trans Electron Dev 50 (2003) 1631-1637
14. Keunwoo K., Fossum J.G., and Te C.C. Process/physics-based threshold voltage model for nano-scaled double-gate devices. Int J Electron 91 March (2004) 139-148
15. Fossum J.G., Ge L., Chiang M.H., Trivedi V.P., Chowdhury M.M., Mathew L., et al. A process/physics-based compact model for nonclassical CMOS device and circuit design. Solid-State Electron 48 6 (2004) 919-926
16. Schulz T., Pacha C., Luyken R.J., Stadele M., Hartwich J., Dreeskornfeld L., et al. Impact of technology parameters on device performance of UTB-SOI CMOS. Solid-State Electron 48 4 (2004) 521-527
17. Shenoy R.S., and Saraswat K.C. Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs. IEEE Trans Nanotechnol 2 (2003) 265-270
18. Trivedi V., Fossum J.G., and Chowdhury M.M. Nanoscale FinFET with gate source/drain underlap. IEEE Trans Electron Dev 52 (2005) 1132-1140
19. Kranti A., and Armstrong G.A. Performance assessment of nanoscale double and triple gate FinFETs. Semicond Sci Technol 21 4 (2006) 409-421
20. Kranti A., and Armstrong G.A. Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: analytical model and design considerations. Solid-State Electron 50 3 (2006) 437-447
21. ATLAS User's Manual-Device Simulation Software: SILVACO International Inc, 2004.
22. Dixit A., Kottantharayil A., Collaert N., Goodwin M., Jurczak M., and De Meyer K. Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans Electron Dev 52 (2005) 56-62
23. MASTAR 4, A user's guide to MASTAR 4, Available on request from STMicroelectronics. Email: thomas.skotnicki@st.com.
24. Ho C.C., Kuo C.W., Chan Y.J., Lien W., and Guo J. 0.13-/spl mu/m RF CMOS and varactors performance optimization by multiple gate layouts. IEEE Trans Electron Dev 51 (2004) 2181-2185
25. Boots H.M.J., Doornbos G., and Heringa A. Scaling of characteristic frequencies in RF CMOS. IEEE Trans Electron Dev 51 (2004) 2102-2108
26. Cheng YH. Advanced MOSFETs Modeling for RF IC Design, NSTI Nanotech 2004, v 2, 2004 NSTI Nanotechnology Conference and Trade show - NSTI Nanotech 2004, vol. 2, 2004. p. 90-5.
27. Eminente S., Alessandrini M., and Fiegna C. Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation. Solid-State Electron 48 4 (2004) 543-549
28. Woerlee P.H., Knitel M.J., van Langevelde R., Klaassen D.B.M., Tiemeijer L.F., Scholten A.J., et al. RF-CMOS performance trends. IEEE Trans Electron Dev 48 (2001) 1776-1782
29. Taur Y. Fundamentals of modern VLSI devices (1998), Cambridge University Press, Cambridge, UK
30. Liou J.J., and Schwierz F. RF MOSFET: recent advances, current status and future trends. Solid-State Electron 47 11 (2003) 1881-1895