Perspectives of fully-depleted SOI transistors down to 20nm gate length

IEEE International SOI Conference

Volumn , Issue , 2002, Pages 137-139

  Luyken, R J ^a   Stadele M ^a   Rosner W ^a   Schulz, T ^a   Hartwich, J ^a   Dreeskornfeld, L ^a   Risch, L ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; MOSFET DEVICES; QUANTUM THEORY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

FULLY-DEPLETED TRANSISTORS;

GATES (TRANSISTOR);

EID: 0036456361     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2002.1044450     Document Type: Conference Paper

References (10)

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10. R. Chau et al., IEDM Tech. Dig. 2001, pp. 621-624.