Double-gate MOSFETs: Is gate alignment mandatory?

European Solid-State Device Research Conference

Volumn , Issue , 2001, Pages 267-270

  Allibert, F ^a,b   Zaslavsky, A ^c   Pretet, J ^a,d   Cristoloveanu, S ^a  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^b PARC TECHNOLOGIQUE DES FONTAINES   (France)

^c CEA LETI   (France)

^d STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE-GATE MOSFETS;

EID: 84907562717     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2001.195252     Document Type: Conference Paper

References (4)

1. J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, 2nd ed., Kluwer, Boston, 1997.
2. J. P. Denton, G. W. Neudeck, "Fully Depleted Dual-Gate Thin-Film SOI PMOSFET's Fabricated on SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, vol. 17, no. 11, Nov 1996.
3. H.-S. P. Wong, K. K. Chan, Y. Taur, "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25nm Thick Silicon Channel", Tech. Digest IEDM, 1997, pp. 427-430.
4. K. Suzuki et al., "High-Speed and Low Power n+-p+ Double-Gate SOI CMOS", IEICE Trans. Electron., vol. E78-C, 1995, pp. 360-367.