Scaling issues for analogue circuits using Double Gate SOI transistors

Solid-State Electronics

Volumn 51, Issue 2, 2007, Pages 320-327

  Lim, Tao Chuan ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Double Gate SOI; Early Voltage; Gate under lapped spacer length; MixedMode simulation; Operational Transconductance Amplifier; Source drain engineering; Transconductance to drain current ratio; Unity gain bandwidth

Indexed keywords

BANDWIDTH; COMPUTER SIMULATION; ELECTRIC POTENTIAL; NETWORKS (CIRCUITS); SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

DOUBLE GATE SOI; EARLY VOLTAGE; GATE UNDER LAPPED SPACER LENGTH; MIXED MODE SIMULATION; OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS; SOURCE DRAIN ENGINEERING; UNITY GAIN BANDWIDTH;

GATES (TRANSISTOR);

EID: 33847331640     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.01.006     Document Type: Article

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