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Volumn 50, Issue 6, 2003, Pages 1552-1555

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

Author keywords

Double gate MOSFET; Lateral solid phase epitaxy; SOI

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRON MOBILITY; TRANSISTORS;

EID: 0042164579     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.813332     Document Type: Article
Times cited : (11)

References (11)
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    • Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices
    • Feb.
    • K. Kim and J. G. Fossum, "Double-gate CMOS: Symmetrical-versus asymmetrical-gate devices," IEEE Trans. Electron Devices, vol. 48, pp. 294-299, Feb. 2001.
    • (2001) IEEE Trans. Electron Devices , vol.48 , pp. 294-299
    • Kim, K.1    Fossum, J.G.2
  • 3
  • 6
    • 0033312227 scopus 로고    scopus 로고
    • Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy
    • Washington, DC
    • J. H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, "Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy," in IEDM Tech. Dig., Washington, DC, 1999, pp. 71-74.
    • (1999) IEDM Tech. Dig. , pp. 71-74
    • Lee, J.H.1    Taraschi, G.2    Wei, A.3    Langdo, T.A.4    Fitzgerald, E.A.5    Antoniadis, D.A.6
  • 7
    • 0034454104 scopus 로고    scopus 로고
    • Novel silicon epitaxy for advanced MOSFET devices
    • G. W. Neudeck, T.-C. Su, and J. P. Denton, "Novel silicon epitaxy for advanced MOSFET devices," in IEDM Tech. Dig., 2000, pp. 169-173.
    • (2000) IEDM Tech. Dig. , pp. 169-173
    • Neudeck, G.W.1    Su, T.-C.2    Denton, J.P.3
  • 8
    • 0036458454 scopus 로고    scopus 로고
    • A high performance double-gate SOI MOSFET using lateral solid-phase epitaxy
    • Williamsburg, VA
    • H. Liu, Z. Xiong, J. K. O. Sin, P. Xuan, and J. Bokor, "A high performance double-gate SOI MOSFET using lateral solid-phase epitaxy," in Proc. IEEE Int. SOI Conf., Williamsburg, VA, 2002, pp. 28-29.
    • (2002) Proc. IEEE Int. SOI Conf. , pp. 28-29
    • Liu, H.1    Xiong, Z.2    Sin, J.K.O.3    Xuan, P.4    Bokor, J.5
  • 9
    • 0035714854 scopus 로고    scopus 로고
    • A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)
    • M. Kumar, H. Liu, J. K. O. Sin, J. K. O. Jun Wan, and K. L. Wang, "A 3-D BiCMOS technology using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE)," in IEDM Tech. Dig., 2001, pp. 729-732.
    • (2001) IEDM Tech. Dig. , pp. 729-732
    • Kumar, M.1    Liu, H.2    Sin, J.K.O.3    Jun Wan, J.K.O.4    Wang, K.L.5
  • 10
    • 0030103268 scopus 로고
    • Enhanced growth mechanism in lateral solid phase epitaxy of Si films simultaneously doped with P and Ge atoms
    • J. H. Oh, C. J. Kim, and H. Ishiwara, "Enhanced growth mechanism in lateral solid phase epitaxy of Si films simultaneously doped with P and Ge atoms," Jpn. J. Appl. Phys., vol. 35, no. 3, pp. 1605-1610, 1995.
    • (1995) Jpn. J. Appl. Phys. , vol.35 , Issue.3 , pp. 1605-1610
    • Oh, J.H.1    Kim, C.J.2    Ishiwara, H.3
  • 11
    • 0033901411 scopus 로고    scopus 로고
    • Nanosacle ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel
    • Apr.
    • Y. C. Yeo, V. Subranmanian, J. Kedzierski, P. Xuan, T. J. King, J. Bokor, and C. Hu, "Nanosacle ultra-thin-body silicon-on-insulator P-MOSFET with a SiGe/Si heterostructure channel," IEEE Electron Device Lett., vol. 21, pp. 161-163, Apr. 2000.
    • (2000) IEEE Electron Device Lett. , vol.21 , pp. 161-163
    • Yeo, Y.C.1    Subranmanian, V.2    Kedzierski, J.3    Xuan, P.4    King, T.J.5    Bokor, J.6    Hu, C.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.