Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

Solid-State Electronics

Volumn 51, Issue 5, 2007, Pages 655-661

  Moldovan, Oana ^a   Cerdeira, Antonio ^b   Jiménez, David ^c   Raskin, Jean Pierre ^d   Kilchytska, Valeria ^d   Flandre, Denis ^d   Collaert, Nadine ^e   Iñiguez, Benjamin ^a  

^a UNIVERSITAT ROVIRA I VIRGILI   (Spain)

^b DEPARTAMENTO DE FÍSICA   (Mexico)

^c UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^d UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

^e IMEC   (Belgium)

Author keywords

Compact device modelling; Double gate MOSFET; Intrinsic capacitances; Parasitic capacitances

Indexed keywords

CAPACITANCE; DOPING (ADDITIVES); ELECTRIC POTENTIAL; FINITE ELEMENT METHOD; SILICON ON INSULATOR TECHNOLOGY; TWO DIMENSIONAL;

COMPACT DEVICE MODELLING; DOUBLE GATE MOSFET; INTRINSIC CAPACITANCES; PARASITIC CAPACITANCES;

MOSFET DEVICES;

EID: 34248594084     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.02.039     Document Type: Article

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