Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime

Solid-State Electronics

Volumn 47, Issue 7 SPEC., 2003, Pages 1199-1203

  Luyken, R J ^a   Schulz, T ^a   Hartwich, J ^a   Dreeskornfeld, L ^a   Stadele M ^a   Rosner W ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFUSION; GATES (TRANSISTOR); SEMICONDUCTOR DOPING;

DRIFT-DIFFUSION SIMULATIONS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0038079337     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00038-8     Document Type: Conference Paper

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