Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

Microelectronic Engineering

Volumn 84, Issue 12, 2007, Pages 2775-2784

  Kranti, Abhinav ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

Cut off frequency; Early voltage; Gate capacitances; Intrinsic voltage gain; Low voltage low power analog applications; Nanoscale double gate SOI MOSFET; Source drain extension region engineering; Transconductance to current ratio

Indexed keywords

ANALOG CIRCUITS; CUTOFF FREQUENCY; DRAIN CURRENT; ELECTRIC POTENTIAL; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

DRAIN EXTENSION REGION ENGINEERING; GATE CAPACITANCES; INTRINSIC VOLTAGE GAIN; LOW-POWER ANALOG APPLICATIONS; TRANSCONDUCTANCE-TO-CURRENT RATIO;

MOSFET DEVICES;

EID: 36148971653     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2007.01.157     Document Type: Article

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