Vertically integrated SOI circuits for low-power and high-performance applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 3, 2002, Pages 351-362

  Wei, Liqiong ^a,b   Zhang, Rongtian ^c   Roy, Kaushik ^a,c   Chen, Zhanping ^a,b   Janes, David B ^a,c  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Delay; Digital CMOS; High performance; High speed interconnect; Low voltage; Low power design; Three dimensional (3 D) circuits

Indexed keywords

DOUBLE-GATE DYNAMIC THRESHOLD; HIGH-SPEED INTERCONNECT; LOW-POWER DESIGN;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC POTENTIAL; MOSFET DEVICES; THREE DIMENSIONAL;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0036625399     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.1043338     Document Type: Article

References (25)

1. L. Wei, Z. Chen, and K. Roy, "Double gate dynamic threshold voltages (DGDT) SOI MOSFET's for low power high performance design," in IEEE Int. SOI Conf., 1997, pp. 82-83.
2. ____, "Design and optimization of dual-gate SOI MOSFET's for low voltage low power CMOS circuits," in 1998 Int. SOI Conf., 1998, pp. 69-70.
3. R. Zhang, K. Roy, and D. B. Janes, "Architecture and performance of 3-dimensional SOI circuits," Proc. 1999 IEEE Int. SOI Conf., pp. 44-45, 1999.
4. M. Bohr, "MOS transistor: Scaling and performance trend," Semiconductor Int., pp. 75-78, June 1995.
5. ____, "Interconnect scaling - The real limiter to high performance ULSI," in Technical Dig. Int. Electron Device Meeting, 1995, pp. 241-244.
6. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
7. International Technology Roadmap for Semiconductors, 1999.
8. J. P. Colinge, Silicon on Insulator Technology: Materials to VLSI. Norwood, MA: Kluwer, 1991.
9. J. P. Denton and G. W. Neudeck, "Fully depleted dual-gate thin-film SOI PMOSFET with an isolated buried polysilicon backgate," in IEEE Int. SOI Conf., 1995, pp. 135-136.
10. R. Zingg, J. A. Friedrich, G. W. Neudeck, and B. Hofflinger, "Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth," IEEE Trans. Electron Devices, vol. 37, pp. 1452-1461, 1990.
11. G. W. Neudeck, S. Pae, J. P. Denton, and T. Sue, "Multiple layers of silicon-on-insulator for nanostructure devices," J. Vacuum Sci. Technol. B, vol. 17, no. 3, pp. 994-998, 1999.
12. J. F. Gibbsons and K. F. Lee, "One-gate-wide CMOS inverter on laser-recrystallized polysilicon," IEEE Trans. Electron Device Lett., vol. EDL-2, pp. 117-118, 1980.
13. K. Suzuki, T. Sugii, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 2326-2329, 1993.
14. A. Tero and F. Van de Wiele, "An analytical model for GAA transistors," Microelectronic Eng., vol. 15, pp. 233-236, Oct. 1991.
15. R. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, 1992.
16. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, "Modeling of ultra-thin double-gate nMOS/SOI transistors," IEEE Trans. Electron Devices, vol. 41, pp. 715-719, 1994.
17. J. G. Fossum et al., SOISPICE-4 (ver. 4.4) user's guide, Univ. of Florida Press, Gainsville, FL, 1998.
18. S. J. Abou-Samra, P. A. Aisa, A. Guyot, and B. Coutois, "3D CMOS SOI for high performance computing," in Proc. 1998 Int. Symp. on Low-Power Electronics and Design, CA, 1998, pp. 54-58.
19. F. Assaderaghi, et al., "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in IEEE Int. Electron Devices Meeting, 1994, pp. 809-812.
20. S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, "Three-dimensional CMOS IC's fabricated by using beam recrystallization," IEEE Trans. Electron Device Letters, vol. EDL-4, pp. 366-368, 1983.
21. K. Sarawat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, "Novel 3D structures," in Proc. 1999 Int. SOI Conf., 1999, pp. 54-55.
22. C. Hu, "Device and technology impact on low power electronics," in Low Power Design Methodologies, J. M. Rabaey and M. Pedram, Eds. Norwell, MA: Kluwer, 1996, pp. 21-36.
23. L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in Int. Electron Device Meeting, 2000, pp. 719-722.
24. R. Zhang, K. Roy, C.-K. Koh, and D. B. Janes, "Stochastic wire-length and delay distributions for 3-dimensional circuits," in Proc. Int. Conf. on Computer-Aided Design, 2000, pp. 208-213.
25. ____, "Power trend and performance characterization of 3-dimensional circuits for future technology generations," in Proc. Int. Symp. Quality Electronic Design, 2001, pp. 217-222.