16nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 637-640

  Boeuf, F ^a   Skotnicki, T ^a   Monfray, S ^a   Julien, C ^a   Dutartre, D ^a   Martins, J ^a   Mazoyer, P ^a   Palla, R ^a   Tavel, B ^a   Ribot, P ^a   Sondergard, E ^a   Sanquer, M ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COULOMB BLOCKADE; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; QUANTUM THEORY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; TRANSMISSION ELECTRON MICROSCOPY;

ADAPTED CHANNEL DOPING; NON-OVERLAPPING GATES;

MOSFET DEVICES;

EID: 0035718151     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)