Analysis of the parasitic S/D resistance in multiple-gate FETs

IEEE Transactions on Electron Devices

Volumn 52, Issue 6, 2005, Pages 1132-1140

  Dixit, Abhisek ^a,b   Kottantharayil, Anil ^a   Collaert, Nadine ^a   Goodwin, Mike ^c   Jurczak, Malgorzata ^a   De Meyer, Kristin ^a,b  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

(110) transport; Analytical model; Fin field effect transistors (FinFETs); Fully depleted; Series resistance; Silicon epitaxy; Silicon on insulator (SOI) MOSFET; Small geometry; Source drain (S D)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; EPITAXIAL GROWTH; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICON ON INSULATOR TECHNOLOGY;

ANALYTICAL MODEL; FIN FIELD EFFECT TRANSISTORS (FINFETS); SERIES RESISTANCE; SILICON EPITAXY; SMALL GEOMETRY; SOURCE/DRAIN (S/D) RESISTANCE;

MOSFET DEVICES;

EID: 21044449128     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.848098     Document Type: Article

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