Device design considerations for nanoscale double and triple gate FinFETs

Proceedings - IEEE International SOI Conference

Volumn 2005, Issue , 2005, Pages 96-98

  Kranti, Abhinav ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33744723744     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2005.1563549     Document Type: Conference Paper

References (11)

1. http://public.itrs.net
2. B.S Doyle et al., IEEE EDL, 24, 263-265, 2003.
3. J.-T. Park et al. IEEE TED, 49, 2222-2228, 2002.
4. V. Trivedi et al., IEEE TED, 52, 56-62, 2005.
5. S.H Kim et al., IEEE SOI Conference, 145-147, 2004.
6. ATLAS Users manual: SILVACO International 2004.
7. K. Banoo et al., Solid-State Electronics 44, 1689-1695, 2000.
8. T.C. Lim et al., Solid-State Electronics, 49, 1034-1043.
9. R.S. Shenoy et al., IEEE Nanotechnology, 2, 265-270, 2003.
10. E. Leobandung et al., J. Vac. Sci. Technol. B, 15, 2791-2794, 1997.
11. T-L Li et al., IEEE TED, 52, 1172-1179.