Modeling advanced FET technology in a compact model

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 1971-1977

  Dunga, Mohan V ^b   Lin, Chung Hsun ^a,b   Xi, Xuemei ^a,b   Lu, Darsen D ^b   Niknejad, Ali M ^a,b   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Berkeley short channel insulated gate FET model (BSIM); Compact modeling, dielectrics; Double gate MOSFETS (DG MOSFETS); High k; MOSFET; Process induced strain

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; INTEGRATED CIRCUIT LAYOUT; PERMITTIVITY; VLSI CIRCUITS;

BERKELEY SHORT CHANNEL INSULATED-GATE FET MODEL (BSIM); COMPACT MODELING; DOUBLE GATE MOSFETS; PROCESS INDUCED STRAIN;

MOSFET DEVICES;

EID: 33947189556     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.881001     Document Type: Article

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