Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 131-134

  Kranti, A ^a   Chung, T M ^a   Flandre, D ^a   Raskin, J P ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG APPLICATIONS; ASYMMETRIC CHANNEL; DOUBLE GATE; FULLY DEPLETED; SOI-MOSFETS;

EID: 84907704345     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256828     Document Type: Conference Paper

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