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Volumn 1, Issue 1, 2002, Pages 56-62

Nanotechnology goals and challenges for electronic applications

Author keywords

Carbon nanotube; Complimentary metal oxide semiconductor (CMOS); Dynamic random access memory (DRAM); Logic; Memory, metal oxide semiconductor (MOS); Metal oxide semiconductor field effect transistor (MOSFET); Molecular electronics; Nanotechnology; Nanowire

Indexed keywords

DYNAMIC RANDOM ACCESS MEMORY (DRAM); MOLECULAR ELECTRONICS; NANOWIRE; SUBTHRESHOLD LEAKAGE;

EID: 0038233833     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2002.1005426     Document Type: Article
Times cited : (187)

References (62)
  • 1
    • 0034429639 scopus 로고    scopus 로고
    • A GHz IA-32 architecture microprocessor implemented on 0.18μm technology with aluminum interconnect
    • P. Green, "A GHz IA-32 architecture microprocessor implemented on 0.18μm technology with aluminum interconnect," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 2000, pp. 98-99.
    • (2000) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 98-99
    • Green, P.1
  • 4
    • 0035054909 scopus 로고    scopus 로고
    • Physical design of a fourth-generation POWER GHz microprocessor
    • C. Anderson et al., "Physical design of a fourth-generation POWER GHz microprocessor," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 2001, pp. 232-233.
    • (2001) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 232-233
    • Anderson, C.1
  • 5
    • 0035063030 scopus 로고    scopus 로고
    • A 1.2 GHz alpha microprocessor with 44.8GB/s chip pin bandwidth
    • A. Jain et al., "A 1.2 GHz alpha microprocessor with 44.8GB/s chip pin bandwidth," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 2001, pp. 240-241.
    • (2001) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 240-241
    • Jain, A.1
  • 7
    • 0002914144 scopus 로고    scopus 로고
    • A 250Mb/s/pin 1Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme
    • Y. Takai et al., "A 250Mb/s/pin 1Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 1999, pp. 418-419.
    • (1999) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 418-419
    • Takai, Y.1
  • 9
    • 0035054744 scopus 로고    scopus 로고
    • A 3.3V 1Gb multi-level NAND flash memory with nonuniform threshold voltage distribution
    • T. Cho et al., "A 3.3V 1Gb multi-level NAND flash memory with nonuniform threshold voltage distribution," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 2001, pp. 28-29.
    • (2001) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 28-29
    • Cho, T.1
  • 11
    • 0029322021 scopus 로고
    • MOS transistors: Scaling and performance trends
    • June
    • M. Bohr, "MOS transistors: Scaling and performance trends," Semicond. Int., vol. 6, pp. 75-80, June 1995.
    • (1995) Semicond. Int. , vol.6 , pp. 75-80
    • Bohr, M.1
  • 12
    • 0033352174 scopus 로고    scopus 로고
    • A 1.2V, Sub-0.09μm gate length CMOS technology
    • M. Mehrotra et al., "A 1.2V, Sub-0.09μm gate length CMOS technology," in Proc. IEDM Tech. Dig., 1999, pp. 419-422.
    • (1999) Proc. IEDM Tech. Dig. , pp. 419-422
    • Mehrotra, M.1
  • 13
    • 0033339637 scopus 로고    scopus 로고
    • Sub-60 nm physical gate length SOI CMOS
    • I. Yang et al., "Sub-60 nm physical gate length SOI CMOS," in Proc. IEDM Tech. Dig., 1999, pp. 431-434.
    • (1999) Proc. IEDM Tech. Dig. , pp. 431-434
    • Yang, I.1
  • 14
    • 0033712801 scopus 로고    scopus 로고
    • A 70 nm gate length CMOS technology with 1.0V operation
    • A. Ono et al., "A 70 nm gate length CMOS technology with 1.0V operation," in Proc. VLSI Technology Dig., 2000. pp. 14-15.
    • (2000) Proc. VLSI Technology Dig. , pp. 14-15
    • Ono, A.1
  • 15
    • 0003899569 scopus 로고    scopus 로고
    • 30nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
    • R. Chau et al., "30nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," in Proc. IEDM Tech. Dig., 2000, pp. 45-18.
    • (2000) Proc. IEDM Tech. Dig. , pp. 45-118
    • Chau, R.1
  • 16
    • 0034454556 scopus 로고    scopus 로고
    • 45-nm gate length CMOS technology and beyond using steep halo
    • H. Wakabayashi et al., "45-nm gate length CMOS technology and beyond using steep halo," in Proc. IEDM Tech. Dig., 2000, pp. 49-52.
    • (2000) Proc. IEDM Tech. Dig. , pp. 49-52
    • Wakabayashi, H.1
  • 17
    • 0034448253 scopus 로고    scopus 로고
    • CMOS device scaling beyond 100nm
    • S. Song et al., "CMOS device scaling beyond 100nm," in Proc. IEDM Tech. Dig., 2000, pp. 235-238.
    • (2000) Proc. IEDM Tech. Dig. , pp. 235-238
    • Song, S.1
  • 18
    • 0034452603 scopus 로고    scopus 로고
    • A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects
    • S. Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects," in Proc. IEDM Tech. Dig., 2000, pp. 567-570.
    • (2000) Proc. IEDM Tech. Dig. , pp. 567-570
    • Tyagi, S.1
  • 19
    • 0035716617 scopus 로고    scopus 로고
    • A high density 0.10μm CMOS technology using low K dielectric and copper interconnect
    • S. Parihar et al., "A high density 0.10μm CMOS technology using low K dielectric and copper interconnect," in Proc. IEDM Tech. Dig., 2001, pp. 249-252.
    • (2001) Proc. IEDM Tech. Dig. , pp. 249-252
    • Parihar, S.1
  • 20
    • 0035714396 scopus 로고    scopus 로고
    • High performance sub-40nm CMOS devices on SOI for the 70nm technology node
    • S. Narashima et al., "High performance sub-40nm CMOS devices on SOI for the 70nm technology node," in Proc. IEDM Tech. Dig., 2001, pp. 625-628.
    • (2001) Proc. IEDM Tech. Dig. , pp. 625-628
    • Narashima, S.1
  • 21
    • 0035718185 scopus 로고    scopus 로고
    • Gate length scaling accelerated to 30nm regime using ultra-thin film PD-SOI Technology
    • S. Fung et al., "Gate length scaling accelerated to 30nm regime using ultra-thin film PD-SOI Technology," in Proc. IEDM Tech. Dig., 2001. pp. 629-632.
    • (2001) Proc. IEDM Tech. Dig. , pp. 629-632
    • Fung, S.1
  • 22
    • 17644440986 scopus 로고    scopus 로고
    • A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications
    • A. Perera et al., "A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications," in Proc. IEDM Tech. Dig., 2000. pp. 571-574.
    • (2000) Proc. IEDM Tech. Dig. , pp. 571-574
    • Perera, A.1
  • 23
    • 0035715842 scopus 로고    scopus 로고
    • An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 v
    • S. Thompson et al., "An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V," in Proc. IEDM Tech. Dig., 2001, pp. 257-260.
    • (2001) Proc. IEDM Tech. Dig. , pp. 257-260
    • Thompson, S.1
  • 24
    • 0035714324 scopus 로고    scopus 로고
    • A high performance 0.13 μm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL
    • J. Sleight et al., "A high performance 0.13 μm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL," in Proc. IEDM Tech. Dig., 2001, pp. 245-248.
    • (2001) Proc. IEDM Tech. Dig. , pp. 245-248
    • Sleight, J.1
  • 25
    • 0034454866 scopus 로고    scopus 로고
    • A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications
    • K. Young et al., "A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications," in Proc. IEDM Tech. Dig., 2000, pp. 563-566.
    • (2000) Proc. IEDM Tech. Dig. , pp. 563-566
    • Young, K.1
  • 26
    • 0028590421 scopus 로고
    • Experimental 2.0V power/performance optimization of a 3.6V-design CMOS microprocessor - PowerPC 601
    • J. Bertsch, K. Bernstein, L. Heller, E. Nowak, and F. White, "Experimental 2.0V power/performance optimization of a 3.6V-design CMOS microprocessor - PowerPC 601," in Proc. VLSI Technology Dig., 1994, pp. 83-84.
    • (1994) Proc. VLSI Technology Dig. , pp. 83-84
    • Bertsch, J.1    Bernstein, K.2    Heller, L.3    Nowak, E.4    White, F.5
  • 27
    • 84941607696 scopus 로고
    • Integration of power LDMOS into a low-voltage 0.5 μm BiCMOS technology
    • P. Tsui, P. Gilbert, and S. Sun, "Integration of power LDMOS into a low-voltage 0.5 μm BiCMOS technology," in Proc. IEDM Tech. Dig., 1992, pp. 27-30.
    • (1992) Proc. IEDM Tech. Dig. , pp. 27-30
    • Tsui, P.1    Gilbert, P.2    Sun, S.3
  • 28
    • 84941528947 scopus 로고
    • High-performance 0.5μm CMOS technology for logic LSI's with embedded large capacity SRAMs
    • M. Norishima et al., "High-performance 0.5μm CMOS technology for logic LSI's with embedded large capacity SRAMs," in Proc. IEDM Tech. Dig., 1992, pp. 489-492.
    • (1992) Proc. IEDM Tech. Dig. , pp. 489-492
    • Norishima, M.1
  • 29
    • 0035716168 scopus 로고    scopus 로고
    • Ultrathin high-K gate stacks for advanced CMOS devices
    • E. Gusev et al., "Ultrathin high-K gate stacks for advanced CMOS devices," in Proc. IEDM Tech. Dig., 2001, pp. 451-454.
    • (2001) Proc. IEDM Tech. Dig. , pp. 451-454
    • Gusev, E.1
  • 30
    • 0035718371 scopus 로고    scopus 로고
    • 2 as high-k gate dielectrics with polysilicon gate electrode
    • 2 as high-k gate dielectrics with polysilicon gate electrode," in Proc. IEDM Tech. Dig., 2001, pp. 455-458.
    • (2001) Proc. IEDM Tech. Dig. , pp. 455-458
    • Kim, Y.1
  • 32
    • 0032164821 scopus 로고    scopus 로고
    • Modeling statistical dopant fluctuations in MOS transistors
    • Sept.
    • P. Stolk, F. Widdershoven, and D. Klaassen, "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sept. 1998.
    • (1998) IEEE Trans. Electron Devices , vol.45 , pp. 1960-1971
    • Stolk, P.1    Widdershoven, F.2    Klaassen, D.3
  • 33
    • 0033281305 scopus 로고    scopus 로고
    • Monte Carlo modeling of threshold variation due to dopant fluctuations
    • D. Frank, Y. Yaur, M. Ieong, and H. Wong, "Monte Carlo modeling of threshold variation due to dopant fluctuations," in Symp. VLSI Technology Dig., 1999. pp. 169-170.
    • (1999) Symp. VLSI Technology Dig. , pp. 169-170
    • Frank, D.1    Yaur, Y.2    Ieong, M.3    Wong, H.4
  • 35
    • 0035717948 scopus 로고    scopus 로고
    • Sub-20nm CMOS FinFET technologies
    • Y. Choi et al., "Sub-20nm CMOS FinFET technologies," in Proc. IEDM Tech. Dig., 2001, pp. 421-424.
    • (2001) Proc. IEDM Tech. Dig. , pp. 421-424
    • Choi, Y.1
  • 36
    • 0035714368 scopus 로고    scopus 로고
    • Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits
    • K. Guarini et al., "Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits," in Proc. IEDM Tech. Dig., 2001, pp. 425-428.
    • (2001) Proc. IEDM Tech. Dig. , pp. 425-428
    • Guarini, K.1
  • 38
    • 33646900503 scopus 로고    scopus 로고
    • Device scaling limits of Si MOSFETs and their application dependencies
    • Mar.
    • D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Mar. 2001.
    • (2001) Proc. IEEE , vol.89 , pp. 259-288
    • Frank, D.1    Dennard, R.2    Nowak, E.3    Solomon, P.4    Taur, Y.5    Wong, H.6
  • 39
    • 0035860451 scopus 로고    scopus 로고
    • Limits on silicon nanoelectronics for terascale integration
    • Sept. 14
    • J. Meindl, Q. Chen, and J. Davis, "Limits on silicon nanoelectronics for terascale integration," Science, vol. 293, pp. 2044-2049, Sept. 14, 2001.
    • (2001) Science , vol.293 , pp. 2044-2049
    • Meindl, J.1    Chen, Q.2    Davis, J.3
  • 40
    • 0035054933 scopus 로고    scopus 로고
    • Microprocessors for the new millennium: Challenges, opportunities, and new frontiers
    • P. Gelsinger, "Microprocessors for the new millennium: Challenges, opportunities, and new frontiers," in Proc. IEEE Int. Solid-State Circuits Conf. Dig., 2001, pp. 22-25.
    • (2001) Proc. IEEE Int. Solid-state Circuits Conf. Dig. , pp. 22-25
    • Gelsinger, P.1
  • 41
    • 0029547914 scopus 로고
    • Interconnect scaling: The real limiter to high performance ULSI
    • M. Bohr, "Interconnect scaling: The real limiter to high performance ULSI." in Proc. IEDM Tech. Dig., 1995, pp. 241-244.
    • (1995) Proc. IEDM Tech. Dig. , pp. 241-244
    • Bohr, M.1
  • 42
    • 0035716692 scopus 로고    scopus 로고
    • Interconnect device opportunities for gigascale integration (GSI)
    • J. Meindl et al., "Interconnect device opportunities for gigascale integration (GSI)," in Proc. IEDM Tech. Dig., 2001, pp. 525-528.
    • (2001) Proc. IEDM Tech. Dig. , pp. 525-528
    • Meindl, J.1
  • 43
    • 0032272377 scopus 로고    scopus 로고
    • Future directions for DRAM memory cell technology
    • A. Nitayama, Y. Kohyama, and K. Hieda, "Future directions for DRAM memory cell technology," in Proc. IEDM Tech. Dig., 1998, pp. 355-358.
    • (1998) Proc. IEDM Tech. Dig. , pp. 355-358
    • Nitayama, A.1    Kohyama, Y.2    Hieda, K.3
  • 45
    • 0034800295 scopus 로고    scopus 로고
    • 2 1T1C COB cell for high density FRAM
    • 2 1T1C COB cell for high density FRAM," in Symp. VLSI Technology Dig., 2001, pp. 111-112.
    • (2001) Symp. VLSI Technology Dig. , pp. 111-112
    • Lee, S.1
  • 46
    • 0034796394 scopus 로고    scopus 로고
    • A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure
    • T. Ozaki et al., "A fully planarized 8M bit ferroelectric RAM with 'chain' cell structure," in Symp. VLSI Technology Dig., 2001, pp. 113-114.
    • (2001) Symp. VLSI Technology Dig. , pp. 113-114
    • Ozaki, T.1
  • 48
    • 0035714650 scopus 로고    scopus 로고
    • 0.1 μm-rule MRAM development using double-layered hard mask
    • K. Tsuji et al., "0.1 μm-rule MRAM development using double-layered hard mask," in Proc. IEDM Tech. Dig., 2001, pp. 799-802.
    • (2001) Proc. IEDM Tech. Dig. , pp. 799-802
    • Tsuji, K.1
  • 49
    • 0035717521 scopus 로고    scopus 로고
    • OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications
    • S. Lai and T. Lowrey, "OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications," in Proc. IEDM Tech. Dig., 2001, pp. 803-806.
    • (2001) Proc. IEDM Tech. Dig. , pp. 803-806
    • Lai, S.1    Lowrey, T.2
  • 50
    • 0035834444 scopus 로고    scopus 로고
    • Logic circuits with carbon nanotube transistors
    • Nov. 9
    • A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, pp. 1317-1320, Nov. 9, 2001.
    • (2001) Science , vol.294 , pp. 1317-1320
    • Bachtold, A.1    Hadley, P.2    Nakanishi, T.3    Dekker, C.4
  • 51
    • 0035718181 scopus 로고    scopus 로고
    • Carbon nanotube field effect transistors for logic applications
    • R. Martel, H. Wong, K. Chan, and P. Avouris, "Carbon nanotube field effect transistors for logic applications," in Proc. IEDM Tech. Dig., 2001, pp. 159-162.
    • (2001) Proc. IEDM Tech. Dig. , pp. 159-162
    • Martel, R.1    Wong, H.2    Chan, K.3    Avouris, P.4
  • 52
    • 0035834415 scopus 로고    scopus 로고
    • Logic gates and computation from assembled nanowire building blocks
    • Nov. 9
    • Y. Huang, X. Duan, Y. Cui, L. Lauhon, K. Kim, and C. Lieber, "Logic gates and computation from assembled nanowire building blocks," Science, vol. 294, pp. 1313-1317, Nov. 9, 2001.
    • (2001) Science , vol.294 , pp. 1313-1317
    • Huang, Y.1    Duan, X.2    Cui, Y.3    Lauhon, L.4    Kim, K.5    Lieber, C.6
  • 53
    • 0001006105 scopus 로고    scopus 로고
    • Single-electron transistor logic
    • Apr. 1
    • R. Chen, A. Korotkov, and K. Likharev, "Single-electron transistor logic," Appl. Phys. Lett., vol. 68, pp. 1954-1956, Apr. 1, 1996.
    • (1996) Appl. Phys. Lett. , vol.68 , pp. 1954-1956
    • Chen, R.1    Korotkov, A.2    Likharev, K.3
  • 54
    • 0034447263 scopus 로고    scopus 로고
    • Room-temperature operation of multifunctional single-electron transistor logic
    • K. Uchida, J. Koga, R. Ohba, and A. Toriumi, "Room-temperature operation of multifunctional single-electron transistor logic," in Proc. IEDM Tech. Dig., 2000, pp. 863-865.
    • (2000) Proc. IEDM Tech. Dig. , pp. 863-865
    • Uchida, K.1    Koga, J.2    Ohba, R.3    Toriumi, A.4
  • 55
    • 0035246552 scopus 로고    scopus 로고
    • Si nanocrystal memory cell with room-temperature single electron effects
    • Feb.
    • I. Kim, S. Han, K. Han, J. Lee, and H. Shin, "Si nanocrystal memory cell with room-temperature single electron effects," Jpn. J. Appl. Phys., pt. 1, vol. 40, no. 2A, pp. 447-451, Feb. 2001.
    • (2001) Jpn. J. Appl. Phys., Pt. 1 , vol.40 , Issue.2 A , pp. 447-451
    • Kim, I.1    Han, S.2    Han, K.3    Lee, J.4    Shin, H.5
  • 56
    • 0035714269 scopus 로고    scopus 로고
    • Silicon single-electron memory & logic devices for room temperature operation
    • J. Koga, R. Ohba, K. Uchida, and A. Toriuma, "Silicon single-electron memory & logic devices for room temperature operation,", in Proc. IEDM Tech. Dig., 2001, pp. 143-146.
    • (2001) Proc. IEDM Tech. Dig. , pp. 143-146
    • Koga, J.1    Ohba, R.2    Uchida, K.3    Toriuma, A.4
  • 57
    • 0035848255 scopus 로고    scopus 로고
    • Experimental demonstration of a latch in clocked quantum-dot cellular automata
    • Mar. 12
    • A. Orlov et al., "Experimental demonstration of a latch in clocked quantum-dot cellular automata," Appl. Phys. Lett., vol. 78, pp. 1625-1627, Mar. 12, 2001.
    • (2001) Appl. Phys. Lett. , vol.78 , pp. 1625-1627
    • Orlov, A.1
  • 58
    • 0012326077 scopus 로고    scopus 로고
    • Single-electron-parametron-based logic devices
    • Dec. 1
    • A. Korotkov and K. Likharev, "Single-electron-parametron-based logic devices," J. Appl. Phys., vol. 84, pp. 6114-6126, Dec. 1, 1998.
    • (1998) J. Appl. Phys. , vol.84 , pp. 6114-6126
    • Korotkov, A.1    Likharev, K.2
  • 59
    • 0033115647 scopus 로고    scopus 로고
    • Molecular-scale electronics
    • Apr.
    • M. Reed, "Molecular-scale electronics," Proc. IEEE, vol. 87, pp. 652-658, Apr. 1999.
    • (1999) Proc. IEEE , vol.87 , pp. 652-658
    • Reed, M.1
  • 60
    • 0033575366 scopus 로고    scopus 로고
    • Electronically configurable molecular-based logic gates
    • July 16
    • C. Collier et al., "Electronically configurable molecular-based logic gates," Science, vol. 285, pp. 391-394, July 16, 1999.
    • (1999) Science , vol.285 , pp. 391-394
    • Collier, C.1
  • 61
    • 0034682887 scopus 로고    scopus 로고
    • A [2]catenane-based solid state electronically reconfigurable switch
    • Aug. 18
    • C. Collier et al., "A [2]catenane-based solid state electronically reconfigurable switch." Science, vol. 289, pp. 1172-1175, Aug. 18, 2000.
    • (2000) Science , vol.289 , pp. 1172-1175
    • Collier, C.1
  • 62
    • 0035824402 scopus 로고    scopus 로고
    • Field-effect modulation of the conductance of single molecules
    • Dec. 6
    • J. Schön, H. Meng, and Z. Bao, "Field-effect modulation of the conductance of single molecules," Science, vol. 294, pp. 2138-2140, Dec. 6, 2001.
    • (2001) Science , vol.294 , pp. 2138-2140
    • Schön, J.1    Meng, H.2    Bao, Z.3


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